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40nm process geometries take a quarter of global wafer capacity

Posted: 05 Apr 2013 ?? ?Print Version ?Bookmark and Share

Keywords:wafer capacity? 40nm process? IC production?

The production of IC devices using process geometries (or feature sizes) smaller than 40nm is more than one fourth of the total installed wafer capacity worldwide, as stated in IC Insights' Global Wafer Capacity report. The report noted that a large chunk of the capacity still remains dedicated to mature processes with "large" features sizes.

Installed capacity is divided into six categories based on the minimum geometry of the processes used in wafer fabrication. The six categories range from <40nm; 40 - <60nm; 60nm - <80nm; 80nm - <0.2?; 0.2? - <0.4?; 0.4?. At the end of 2012, about 27 per cent of global wafer capacity was for devices having geometries smaller than 40nm. Such devices include high-density DRAM, which are typically built using 30nm- to 20nm-class process technologies; high-density flash memory devices that are based on 20nm- to 10nm-class processes; and high-performance microprocessors and advanced ASIC/ASSP/FPGA devices based on 32/28nm or 22nm technologies.

Worldwide capacity

Figure 1: Worldwide capacity by minimum geometry as of December 2012 (installed monthly capacity in 200mm-equiv. wafers x1000)
Source: IC Insights

About 22 per cent of global capacity is dedicated to the 80nm - <0.2? segment, which includes the 90nm, 0.13?, and 0.18? process generations. This "mature" process is widely used by pure-play foundries including TSMC, UMC, GlobalFoundries, SMIC, and TowerJazz and to manufacture a broad range of products for their diverse customer bases.

The least common technologies, at least in terms of the share of total installed capacity, are between the geometries of 80nm and 60nm (essentially the 65nm generation) and between 0.4? and 0.2? (essentially the 0.25? and 0.35? generations). However, it is worth noting that the >0.4? category maintains a fairly large share of total capacity, even though it has been longer than a decade-and-a-half since 0.5? process technology was considered leading-edge. The main reason is that huge quantities of commodity type devices such as standard analog and general-purpose logic are manufactured with well-established process technologies having larger than 0.4? feature sizes. In addition, high-voltage IC products require large-geometry process technologies.

Figure 2 below shows the leading suppliers of installed wafer capacity based on minimum geometry. It is not surprising that Samsung, Intel, Toshiba/SanDisk, SK Hynix, and Micron top the list with the greatest amount of leading-edge capacity. The biggest capacity holders in the large-feature process category (>0.2?) consist of several analog and mixed-signal chip suppliers.

Capacity leaders ranking

Figure 2: Installed capacity leaders per min. geometry as of December 2012 (ranked by shares of total WW installed monthly 200mm-equiv. capacity)
Source: IC Insights





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