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ARM, Cadence to advance IP, design automation

Posted: 10 Apr 2013 ?? ?Print Version ?Bookmark and Share

Keywords:IP? design automation? FinFET?

ARM and Cadence have teamed up to implement the first ARM Cortex-A57 processor on TSMC's 16nm FinFET manufacturing process. The test chip was implemented using the complete Cadence RTL-to-signoff flow, Cadence Virtuoso custom design platform, ARM Artisan standard cell libraries and TSMC's memory macros.

The Cortex-A57 processor is ARM's highest-performing processor to date, and is based on the new ARMv8 architecture, designed for computing, networking and mobile applications that require high performance at a low-power budget, stated the company. TSMC's 16nm FinFET technology is a significant breakthrough that enables continued scaling of process technology to feature sizes below 20nm. This test chip, developed with Cadence's custom, digital and signoff solutions for FinFET process technology, was a collaboration that resulted in several innovations and co-optimisations between manufacturing process, design IP and design tools, the firms indicated.

The 16nm process using FinFET technology presented new challenges that required significant new development in the design tools. New design rules, RC extraction for 3D transistors, increased complexity of resistance models for interconnect and vias, quantised cell libraries, library characterisation that supports new transistor models and double patterning across more layers are some of the challenges that have been addressed in Cadence's custom, digital and signoff products, added the firm.





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