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How to recover lost yield

Posted: 15 Apr 2013 ?? ?Print Version ?Bookmark and Share

Keywords:power density? dynamic voltage drop? yield loss?

As designs are shifting to 28nm and beyond, designers fully experience the effects of the much higher power density and diminishing effectiveness of decoupling capacitances at these geometries. Failures due to dynamic power noise integrity issues is a significant contributor to yield loss in many designs. Synchronous switching and increasing di/dt at advanced process nodes (figure 1) makes it increasingly challenging for designers to deal with on-chip dynamic voltage drop (DVD) and high frequency electromagnetic interference (EMI). And neither is to be taken lightly; studies have shown DVD fluctuations introduce sizable gate delays causing timing-related yield loss, and EMI from digital switching similarly cause mixed-signal yield loss due to compromised noise integrity.

Figure 1: Transient current (di/dt) has increased significantly for each new process node, causing higher dynamic voltage drop and digital switching noise (Source: INSA, Toulouse, France).

Test-mode yield loss due to DVD Designers already deal with a DVD 'budget'. In a study done by Mentor Graphics and company SMIC, measuring failures across 25 designs, 49% of the yield loss was attributed to SCAN/ATPG/function fail defects (figure 2).

To save cost of implementation, an on-chip Power Delivery Network (PDN) is often dimensioned for functional modes; not the worst-case test mode. As the scan test mode results in a higher dynamic power density than functional modes, chips that would work properly in functional mode actually fail in scan test due to the increased DVD. It is somewhat ironic that design methods and tests, which should guarantee more good products and higher profit, themselves contribute to an increasing yield loss.

Figure 2: SCAN/ATPG failure is a significant share of the total yield loss. (Source: Mentor Graphics, Taipei, Taiwan).

Mixed-signal issuesThe integration of digital and analogue/RF circuits in mixed-signal designs has always caused even the best designs C and best designers C substrate noise problems. The impact of the substrate noise relates to the distance between noise aggressor and victim circuit, the layout of the circuit and the behaviour of the digital circuit (magnitude and spectrum of noise). Advanced process nodes, originally only adapted in digital designs, are now being used in mixed-signal products too, putting further pressure on specifications and yield. Digital blocks are increasing in size hence causing more noise. Furthermore, designers have to deal with high-frequency effects of a much steeper di/dt at newer process nodes.

As an example, moving from a 180nm to a 65nm technology, analogue designers have seen substrate noise from synchronously switching digital blocks go up by 18 dB; purely by change of process and without changing architecture or design.

Meanwhile, new product performance requirements put an even higher demand on the mixed-signal design, just look at the modulation schemes in wireless LAN (figure 3).

Figure 3: SCAN/ATPG failure is a significant share of the total yield loss. (Source: Mentor Graphics, Taipei, Taiwan).

Evolving from 802.11b (QPSK) through 802.11ac (256QAM) significant advancements in modulation efficiency and data density was demonstrated. However, the Error Vector Magnitude requirementa measure for the allowed deviation of constellation points, from the required position C has increased significantly: it now needs to be 27 dB better than the original 802.11b specification.

So, as 10's of dBs of noise is being introduced by scaling the process nodes, new applications and standards require much lower on-chip noise than previous generations. This cocktail of high-performance mixed-signal requirements in increasingly noisy environments, is a cocktail doomed for yield degradation.

However, for both mixed-signal and digital designs it is possible to use a systematic optimisation methodology to shape the design's digital power noise signature, and counteract both dynamic voltage drop and on-chip noise to recover the lost yield.

Improving dynamic power integrity and power noise yieldFrom a dynamic power integrity and power noise perspective, the fundamental problem with a synchronous design is exactly that; it's synchronous. Having all flops clocked at (ideally) the same time creates significant power noise integrity problems. But by using a modern EDA back-end optimisation tool like FloorDirector, designers can attack this problem in a systematic and controlled manner. FloorDirector works in the time and frequency domains concurrently. By analysing available timing slack on each single path in each scenario and dynamic power in each use-case, the tool can resolve clock scheduling solutions to shape the current pulse and noise spectrum so that it matches the designer's power or frequency optimisation targets. As all optimisations are within-cycle optimisations, the cycle-to-cycle functionality of the design remains unaltered.

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