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Fujitsu's mobile platform ships out with Synopsys' PHY IP

Posted: 15 Apr 2013 ?? ?Print Version ?Bookmark and Share

Keywords:Synopsys? Fujitsu? DesignWare? compliance? base band processor?

Synopsys has recently announced that Fujitsu Semiconductor Limited has successfully shipped a 2G/3G/4G baseband processor using the company's DesignWare DigRFv4 M-PHY and DigRF 3G PHY IP. Fujitsu Semiconductor selected Synopsys' silicon-proven IP to mitigate project schedule risks and help ensure the long-term interoperability of their ASIC design customer's system-on-chip (SoC) with Fujitsu Semiconductor's RFIC products. With the integration of DesignWare IP, Fujitsu Semiconductor was able to deliver an efficient, low-power and cost-effective solution.

"Our customer's next-generation mobile devices required low power, high bandwidth connectivity, so we needed a reliable IP solution in the required process technology that was compliant with MIPI standard specifications," said Daisuke Yamazaki, manager, design department, wireless solution division at Fujitsu Semiconductor. "Integrating Synopsys' DesignWare DigRFv4 M-PHY and DigRF 3G PHY IP helped ensure the successful silicon tape-out and production ramp of mobile SoCs targeting 2G/3G/4G speeds with high data rates and low power consumption."

Fujitsu Semiconductor's ASIC design services customer needed to launch its mobile platform quickly with a low-power 28nm 2G/3G/4G base band product supporting multi-mode, multi-band LTE, UMTS, and EDGE mobile handsets with full support for all global FDD and TDD bands. Since both the target 28nm process technology and the MIPI specifications were being finalized in parallel with the integration of Synopsys' M-PHY into the ASIC, Synopsys and Fujitsu Semiconductor worked closely to maintain clear and consistent communication throughout the product development cycle to ensure a successful tape-out. The engineering teams were able to identify and address differences between the DigRFv4 and DigRF 3G standard specifications, keeping the project schedule on track.





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