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Critical issues for functioning JESD204B interface

Posted: 29 Apr 2013 ?? ?Print Version ?Bookmark and Share

Keywords:JESD204B? JEDEC Standard? serial data interfacing?

JESD204B is a newly approved JEDEC Standard for serial data interfacing between converters and digital processing devices. As a third-generation standard, it addresses some of the limitations of the earlier versions. Among the benefits of this interface are reductions in required board area for data-interface routing, reduces setup and hold timing requirements and enables smaller packages for converter and logic devices. New analogue/digital converters from various vendors, such as the AD9250 from Analog Devices, use this interface.

There is a trade-off to realising the benefits of JESD204B, as it has complexities and subtleties which distinguish it from existing interface formats and protocols. As with any standard, it is clear that the interface must function seamlessly to gain popularity and traction versus more common interfaces, such as single data rate or double data rate CMOS or LVDS. Although the JESD204B standard is documented by JEDEC, some specific information about it is subject to interpretation or may be spread over multiple references. It is also obvious that it would be extremely helpful if there was a concise guide that provided an overview of the standard, how it works, and how to troubleshoot it if issues arise.

This article explains the interface from an ADC to FPGA for JESD204B, how to identify when it's working right, and, perhaps more important, how troubleshoot it if something isn't quite right. The troubleshooting techniques discussed can use commonly available test and measurement equipment including oscilloscopes and logic analysers along with software tools such as the Chipscope from Xilinx or SignalTap from Altera. Interface signalling is also explained to allow a single or multiple approaches to visualise the signalling.

JESD204B overview
The JESD204B standard provides a method to interface one or multiple data converters to a digital-signal processing device (typically, an ADC or DAC to an FPGA) over a higher-speed serial interface compared to the more typical parallel data transfers. The interface, which runs at up to 12.5Gbit/s/Lane, uses a framed serial data link with embedded clock and alignment characters. The interface eases implementation of the data interface of high-speed converters by reducing the number of traces between devices, thus reducing trace-matching requirements, and removing setup- and hold-timing constraint issues. Since a link needs to be established prior to data transfer, there are new challenges and techniques required to identify that the interface is working properly and, if not, what to do.

Starting with a brief explanation of how the standard works. JESD204B use three phases to establish the synchronised link: Code Group Synchronisation (CGS), Initial Lane Synchronisation (ILAS), and Data Transmission Phase. Required signals for the link are a shared reference clock (device clock), at least one differential CML physical data electrical connection (called a lane) and at least one other synchronisation signal (SYNC~ and possibly SYSREF). The signals used depend upon the Subclass:

Subclass 0 uses Device Clock, Lanes and SYNC~

Subclass 1 uses Device Clock, Lanes, SYNC~ and SYSREF

Subclass 2 uses Device Clock, Lanes and SYNC~

Subclass 0 is adequate in many cases and so will be the focus of this article. Subclass 1 and Subclass 2 provide a method to establish deterministic latency. This is important in application when synchronising multiple devices or system synchronisation or fixed latency is required (such as when a system needs a known sampling-edge for an event or an event must react to an input signal within a specified time).

Figure 1 shows a simplified JESD204B Link from the Tx Device (ADC) to the Rx Device (FPGA), with data from one ADC going over one lane.

Figure 1: JESD204B link diagram for 1 ADC to an FPGA through 1 Lane.

Although there are many variables within the JESD204B specification, some have particular importance when establishing a link. These key variables from the specification are (Note: these values are typically represented as 'X-1'):

???M : Number of converters
???L : Number of Physical Lanes
???F: Number of Octets per Frame, also
???K : Number of frames per Multiframe
???N & N' : Converter Resolution and Number of bits used per sample (multiple of 4), respectively. N' value is N value plus control and dummy bits.

Subclass 0: Synchronisation steps
As noted above, many applications can use the relatively simpler Subclass 0 Mode of operation. This is also the easiest mode to establish and for which to verify a link. Subclass 0 uses three phases to establish and monitor synchronisation: CGS Phase, ILAS Phase and Data Phase. The figures associated with each phase present the data in different formats, as they might be seen on an oscilloscope, logic analyser or FPGA virtual I/O analyser such as Xilinx ChipScope or Altera SignalTap.

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