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Sol'n speeds processor design for embedded vision

Posted: 29 Apr 2013 ?? ?Print Version ?Bookmark and Share

Keywords:HAPS? SoC? FPGA-based prototyping?

Synopsys Inc. has rolled out an integrated solution for the acceleration of the design of processors for embedded vision based on the firm's Processor Designer tool set and HAPS FPGA-based prototyping system. According to the company, the Synopsys Embedded Vision Development System allows designers to rapidly explore and tune processor architectures and quickly implement the design on a HAPS FPGA-based prototype.

The Embedded Vision Development System includes pre-verified design examples to help designers quickly implement an ASIP optimised to meet their specific SoC objectives for power consumption and performance. It provides a ready-to-use, modifiable base processor including a full C/C++ compiler that supports all functions provided by the OpenCV library, stated the company. The execution of the compiled code with the automatically-generated instruction-set simulator (ISS) is easy to profile, clearly identifying performance-intensive parts of the application, which can be accelerated by changes in the processor architecture including memory access, register configuration and instruction set, added Synopsys.

Unlike configurable processors that rely on a fixed pipeline and register structure, this methodology removes limitations from achieving the most power- and performance-optimised custom architecture for their application. Using the automatically generated software tools, designers easily recompile and simulate the C/C++ program until they achieve their design goals.

Processor Designer generates optimised RTL of the ASIP, which can easily be downloaded into a HAPS FPGA-based prototyping system. Designers save implementation effort with an easy-to-use flow from RTL generation to instantiation in the HAPS system, using the same RTL from design through validation, the company said. HAPS prototypes allow the design team adopting the application-specific processor to integrate other digital IP into the SoC design and connect the prototype with real-world I/O such as cameras and memory to validate the hardware-software integration. Running more than 100x faster than a cycle-accurate ISS-based model, the combination of Processor Designer and HAPS in the new integrated design and prototyping system provides a highly-efficient way to refine and validate ASIP architectures from project to project, the firm stated.

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