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Why stitch and ship is no longer workable

Posted: 09 May 2013 ?? ?Print Version ?Bookmark and Share

Keywords:system on chips? verification? register transfer level?

Because this approach generates C code, test cases can be run on abstract models, on models implemented at RTL executing in a simulator or accelerated using an emulator. Test cases can be run on the fabricated chip, as well, making it possible to use a single verification methodology throughout the entire development cycle.

In addition, scenario models are where system-level constraints are defined. They naturally define the system-level coverage model showing which use cases have been exercised using which paths through the system.

Tom Feist, senior director of marketing at Xilinx, said in a recent roundtable discussion [2]: "What we provide is a simulator, not a verification tool. You can make RTL work with it. The design methodology needs to focus on reducing the pain, but it has to be done at the architectural level or it's meaningless."

Most electronic design automation (EDA) vendors still continue making tools that focus on the block-level RTL verification problem and have not introduced tools that tackle system-level verification. In contrast, scenario models enable a full solution for the system-level verification problem. It is fully integrated with existing UVM testbench environments such that it can be used to complement existing verification strategies rather than replacing them.

Conclusions
Due to the way in which systems are changing, the stitch and ship methodology is leading to increased numbers of costly failures. The answer is scenario models that define how outcomes can be satisfied within a system. Those outcomes are directly related to the use cases defined in the specifications. Scenario models define intended outcomes, constraints, dependencies and coverage. They provide a scalable solution to the toughest system-level verification problems and can easily augment existing UVM-based verification environments.

References
[1] Marcelo Cataldo and Marcelo Cataldo: "Factors Leading to Integration Failures in Global Feature-Oriented Development: An Empirical Analysis" in Proceedings of the 33rd International Conference on Software Engineering (ICSE 2011), May 21-28, 2011. http://herbsleb.org/web-pubs/pdfs/cataldo-factors-2011.pdf
[2] "Experts at the table: FPGA Prototyping Issues" in System-Level Design Community, September 7, 2012.

http://chipdesignmag.com/sld/blog/2012/09/07/experts-at-the-table-fpga-prototyping-issues-2/

About the author
Adnan Hamid is co-founder and CEO of Breker Verification Systems. Prior to starting Breker in 2003, he worked at AMD as department manager of the System Logic Division. Previously, he served as a member of the consulting staff at AMD and Cadence Design Systems. Hamid graduated from Princeton University with Bachelor of Science degrees in Electrical Engineering and Computer Science and holds an MBA from the McCombs School of Business at The University of Texas.

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