Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
EE Times-Asia > EDA/IP

Synopsys IC compiler update speeds up design closure

Posted: 08 May 2013 ?? ?Print Version ?Bookmark and Share

Keywords:Synopsys? IC Compiler software? FinFET? high-speed design?

Synopsys has recently unveiled the 2013.03 release of its IC Compiler software, a key component of the company's GalaxyImplementation Platform. The latest release features innovations to speed design as well as enables the latest process nodes. New features include advanced optimisations to enable high-speed design, efficient implementation of final-stage engineering change orders (ECO) and fully colour-ready, tape-out-proven support for the emerging FinFET-based silicon processes.

The IC Compiler 2013.03 release includes powerful new features to deliver even faster design closure. One important new capability is the application of final-stage ECOs to close the design.

Working hand-in-hand with the PrimeTimesignoff solution, IC Compiler provides a highly efficient ECO solution rooted in dual principles: first, ensuring that very few ECOs are required after the optimisation steps; and second, applying the ECOs surgically with minimal layout perturbation. In this flow, PrimeTime provides signoff-accurate ECO guidance, implemented using the new minimum physical impact ECO capability, which greatly reduces layout perturbation by reusing wires and minimising device displacement. Combined with a fully automatic, incremental In-Design physical verification capability, IC Compiler provides a significant reduction in turnaround time for ECO closure.

Another area that continues to receive increased attention in advanced chips is clock design. With high-speed designs, the clock distribution network can be a significant contributor to total power. While clock gating is an established technique to minimise clock network power, meeting clock gate timing requirements can be a challenge. Additionally, aggressive clock speeds call for innovative new solutions that combine datapath optimisation with clock cycle adjustment. The 2013.03 IC Compiler release enables high-speed clock design by performing clock estimation during placement to drive physical- and timing-aware clock gating concurrently with clock and data optimisation to achieve the target frequency faster.

IC Compiler 2013.03 delivers these improvements while expanding support for new silicon technology. Since its introduction, IC Compiler has consistently led the way for emerging process node enablement. The previous release of IC Compiler rolled out support for the 20-nm node, which brought many new design challenges including double patterning (DPT). In this latest release, Synopsys' close collaboration with foundries and early adopters to deliver a fully colour-ready, tape-out-proven solution for emerging FinFET-based designs fortifies IC Compiler's strong track record of enabling emerging nodes.

Article Comments - Synopsys IC compiler update speeds u...
*? You can enter [0] more charecters.
*Verify code:


Visit Asia Webinars to learn about the latest in technology and get practical design tips.

Back to Top