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Advantages of surface-mount SSDs

Posted: 13 May 2013 ?? ?Print Version ?Bookmark and Share

Keywords:NOR flash. NAND device? solid state drive?

While not many new embedded processors feature a dedicated IDE disc interface, many of them do have a parallel address and data bus. The generic IDE driver can be easily ported to most embedded controllers, making it a seamless process to connect a surface-mount SSD to a microcontroller via the memory bus.

If we compare the available high-density NOR flash memory device capacities with the capacities of surface-mount SSDs, we can see that the surface-mount SSD comes into its own in capacities above 1 GB. Furthermore, if we examine the memory footprints of popular embedded operating system and application requirements, we can see that this is easily achieved with a single surface-mount SSD.

A typical WinXP Embedded implementation could require 2 GB of storage for operating system (OS), applications and user storage. An implementation with conventional WinXP would require a minimum of 8 GB, which would be very difficult to accomplish using today's NOR flash devices.

What about discrete NAND?
Once we accept that a NAND-based device can meet our goals for capacity, cost and ease of use, it is worth considering whether managed NAND is better than a discrete NAND device. Many embedded processors provide a dedicated NAND interface, and a discrete NAND device could be used on this bus. At first sight, this seems like a simple solution that would allow us to implement the PC-type architecture we have have described above. The major issue, which many designers have faced when adopting this approach, is that the NAND controller supporting this interface is designed to support a specific set of NAND technologies. NAND-flash memory is a developing technology for which the NAND manufacturers are in a race driven by the constant demand for higher capacities and lower costs. This means new geometries and technologies are introduced at a rapid pace which can leave the processor's NAND controller stranded on the start line.

In contrast, a managed NAND device like a surface-mount SSD has the controller and NAND integrated into a single package with a standard interface. This ensures that the embedded system designer can take advantage of the higher capacities and lower costs, but not be caught up in the complexities of implementing the new technologies at a systems level. Another alternative could be something like a low-capacity embedded MultiMediaCard (eMMC) NANDrive with boot capability. This is also a more cost-effective solution compared to the significantly more expensive high-density NOR, but it would require the processor to support an SD/eMMC interface, which many ARM-based processors do today.

Applications suitable for using managed NAND flash in place of NOR flash:

???Set-top box / Net-top box
???GPS and telematics
???In-vehicle infotainment
???Video conferencing
???Multi-function printer
???Point of Sale terminal
???VoIP system / PBX
???Wireless base station
???Router / Gateway / Switch
???Server / Network-attached storage
???Industrial PC / Single-board computer
???Ultrasound and medical imaging
???Industrial automation & control
???Test & measurement instrumentation
???Video surveillance / ID terminal

Surface-mount SSD on the memory bus (PIO mode)
Making a PC-style architecture work in an embedded system requires an embedded surface-mount SSD with the ability to connect to a variety of buses, because most embedded systems will not necessarily have a native IDE/ATA interface available. The key to making it feasible to use a surface-mount SSD on the memory bus is the simplicity of the parallel ATA (PATA) interface. The PATA interface closely resembles a traditional RAM-type memory bus with address, data and control signals. The interface uses three pins for the address of the ATA task-file registers and two chip-select (CS) pins for register set selection. Details of the register functions (command and address information, status and error reporting, etc.) are fully described in the ATA specification. There is a further minimum of 8 bits for the data bus (this can be set to 16 if required) and four additional control lines for Read and Write control, Interrupt Request and Reset. This means that the minimum implementation requires only 17 pins if an 8bit data bus is used. (figure 2).

Figure 2: The similarity of the PATA interface to a traditional RAM-type memory bus simplifies implementation.

Operating system considerations
Operating system driver considerations will depend on whether the host OS already has support for the IDE/ATA protocol on the memory bus. For an OS like Linux, it will be a case of modifying the IDE/ATA control register address and Interrupt mapping to treat the surface-mount SSD as a system peripheral.

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