Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
?
EE Times-Asia > EDA/IP
?
?
EDA/IP??

Performing synthesis-aware clock analysis

Posted: 23 May 2013 ?? ?Print Version ?Bookmark and Share

Keywords:clock tree synthesis? signal integrity? PLL?

In the design of clock networks, both front-end and back-end teams use SDC files to define clocks and to set up design constraints. Today, with multiple clocks and several more generated clocks in every design, several SDC files are created to accommodate all clock circuits for a given design. With the ability to handle only a limited number of modes, CTS tools operate using a clock specification file and one SDC file only. This SDC file is typically a merged version of many SDC files from the front-end team. The SDC file, however, still does not communicate the logical awareness or intentions of the front-end team in its definition of clocks and generated clocks. With the SDC file that drives the CTS tool being different from the SDC files generated by the front-end team, there is a high risk that the final implementation could be different from what was originally intended and designed. This is typically seen at the ECO stage of chip design, delaying and/or forcing the production of a lower-performance chip.

Once the clocks and generated clocks are defined in a SDC file, a clock network will be formed, which becomes a sub-graph of the design netlist. This graph will be trimmed further as per the definitions in the clock specification file, which includes ignore pins, pass-through pins, stop pins, etc. During the CTS process, since the consolidated file is devoid of logical awareness, CTS tools use a tracing function to get an expanded view of a clock network. This becomes the superset and the initial clock graph for balancing. This superset is obviously a view of the clock network and is different from that created by the front-end designers. The expanded network may have non-clock portions in it. Balancing of the non-clock portion of a network is not necessary, and if balanced, it will result in a non-optimal clock tree with unnecessary buffers and hence increased power consumption.

Complex physical design constraints
Due to the endless push for high performance and low power, the physical design of modern SOC chips become more and more complex. Building clock trees on top of such complex physical designs is a challenge.

First, as the size of SOC chips become bigger and bigger, it is not unusual to see 100 million gates in designs. Such designs are usually implemented hierarchically. This requires the clock trees to be built hierarchically as well. Balancing hierarchically built clock trees is difficult.

Second, when process technology scales to 28nm, 20nm, and down to 14nm and 10nm, signal integrity (SI) becomes a difficult issue for physical design and timing closure tools to handle. Since clock signals switch at high frequencies, they are very sensitive to SI issues. Such clock signals are usually shielded or routed using non-default spacing rules to avoid SI issues.

Figure 3: When an always-on clock net traverses across on/off power domain, an always-on buffer is needed for buffer insertion.

Third, use of multi-voltage domains is a popular implementation choice for lower-power SOC designs. In such designs, chip area is partitioned into several voltage domains, such that individual domains can be turned on and off as needed. Typically, each of these domains uses standard cells from different libraries for implementation. Clock trees are the global circuitry in the design. To build a clock tree over voltage domains that are turned on or off as needed is a challenge.

?First Page?Previous Page 1???2???3???4?Next Page?Last Page



Article Comments - Performing synthesis-aware clock ana...
Comments:??
*? You can enter [0] more charecters.
*Verify code:
?
?
Webinars

Seminars

Visit Asia Webinars to learn about the latest in technology and get practical design tips.

?
?
Back to Top