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Performing synthesis-aware clock analysis

Posted: 23 May 2013 ?? ?Print Version ?Bookmark and Share

Keywords:clock tree synthesis? signal integrity? PLL?

These bring up the fact that there is more interdependency between different clock networks on chip. Since the sequence in which constraints are fed into a CTS tool determines the structure and balance of the clock network implementation, it is possible for the back-end SDC file to force a clock implementation that is different from what was intended by the front-end team. The physical considerations that one needs to take into account add another dimension to the implementation of clocks in today's SOC designs.

Addressing clock optimisation issues
The issues discussed above are addressed by the ICScape ClockExplorer tool, which complements a CTS tool and speeds up the physical design closure of clock networks. Built-in analysis and optimisation capabilities of ClockExplorer are:

???A schematic-based clock analysis platform with built-in SDC checking validates the correctness of clock definitions.
???The optimisation of SDC constraints for better CTS includes:
- Invalid clock path checking
- Defining the appropriate CTS sequence through timing dependency analysis
- Detecting conflicts in clock pins, and synthesising with the right sequence and clock specification

Comprehensive clock structure analysis by schematics
ClockExplorer performs clock structure analysis by tracing complex clock nets and visually presenting them to designers. The visual outcome of this analysis, which designers can easily relate to, is a schematic of the clock network. Schematic snapshots of multi-mode clock structures help users to identify clock overlaps and re-convergence. The tracing also helps users to identify the longest and shortest clock paths.

After CTS, clock-timing information is back-annotated on schematics for both front-end and back-end teams to view and analyse. The teams may use cross probing between schematics and design layout to find out a variety of things, including long clock paths, bad placement problems, or need for maximum load fix.

Figure 4: Clock path from PLL to clock root will not be checked or fixed by CTS tools.

SDC constraint checking
SDC files define clock and generated clocks. Inadequately defined clocks may result in incomplete or incorrect clock designs. Improperly defined SDC may also result in unbalanced clock trees that will make timing closure difficult.

The following is a partial list of items that ClockExplorer checks to make sure clocks are defined properly.

1. A clock or a generated clock is defined only on pins in the netlist.
2. Clock root pin is not defined on a chip boundary or a PLL.

In such cases, CTS tools will not check or fix violations on path segments back traced from the clock root pin to the chip boundary or PLL. Timing checks will not find this issue since the inspections are started from the clock root. This may result in an incorrect clock signal at a clock root pin and hence chip failure.

3. Generated clock root pins are correctly defined; otherwise, they cannot be traced back to its clock root.
4. Un-clocked flip-flops are identified. This is usually the result of a missing clock definition or broken clock paths due to SDC constraints such as case analysis.

Reduce CTS clock graph by removing invalid clock paths
An invalid clock path is a clock path where the signal is not a clock signal but is a data signal used for clock gating. Since traced clock signals by CTS tools often include invalid clock paths, ClockExplorer identifies such invalid clock paths and makes sure they are not considered in balancing and hence buffer insertion.

Figure 5: Invalid clock path.


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