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Performing synthesis-aware clock analysis

Posted: 23 May 2013 ?? ?Print Version ?Bookmark and Share

Keywords:clock tree synthesis? signal integrity? PLL?

Figure 5 shows an invalid clock path, ABQCG. When a generated clock is defined at pin G, CTS tools will back trace to the clock root A. Since design information is not available, CTS tools will include path ABQCG as part of the clock graph. Net on QC is not a clock signal but is a type of data and hence is an invalid clock path. The true clock path is AEG. When an invalid clock path exists but is not recognised, CTS tools insert a series of buffers on AEG to match the delay of the flop. This is unnecessary and any buffer inserted is a waste.

The correct approach is to set pin C to be ignored so the invalid path is broken. The resulting clock graph looks like figure 6.

Figure 6: Clock graph after setting ignore pin at C.

Resolving clock specification conflicts between modes
For a given design, typically there are at least two modesone functional mode and one test mode. Between those modes, conflicting clock pin definitions may exist, as illustrated in figure 7.

Figure 7: Conflict clock pin between modes.

In the functional mode, a generated clock is defined at pin Q of the clock divider, Div. This will result in a non-stop pin, Div/CLK, for the functional mode. However, in the test mode, a generated clock is not defined at Div/Q. CTS tools will treat Div/CLK as a leaf pin or stop pin and try to balance the path through Div with all of the other flops FFs1 and FFs2. This is neither possible nor something that designers want. Div is a clock divider and should not be tested by scan, and hence, Div/CLK should be ignored.

The right sequence of steps for a CTS tool is to first synthesise FCLK1 and FCLK2 in the functional mode, and then in the test mode, set Div/CLK to be ignored and synthesise SCLK.

Timing dependency
In a given design, not all flops are connected to each other through combinational logic. Flops so-connected are called timing dependent, and non-connected flops are considered to be timing independent.

Figure 8: Timing-dependent flop groups.

During CTS, only dependent flops should be balanced. Balancing independent flops is not necessary, and in addition, it consumes unnecessary power. Therefore, the right CTS flow is to first run timing dependency analysis and then balance the dependent groups separately (refer to figure 8) as follows:
???Set Y1 as the ignore pin.
???Synthesise the clock tree root at Y2.
???Set the clock tree at Y2 as do not touch.
???Synthesise the clock tree root at CLK (root).

Bridge the gap between front-end and back-end teams
ClockExplorer is architected to bridge the knowledge gap between front-end design and back-end implementation teams. The front-end team uses this platform to perform clock analysis, SDC, and clock constraints sign-off. The back-end team uses ClockExplorer to complete the sign-in verification and checking.

Figure 9: ClockExplorer bridges communication gap.

The front-end clock sign-off includes:
???SDC checking
???Clock specification checking
???Mode conflict checking

The back-end clock sign-in includes:

???SDC checking
???Clock specification checking
???Invalid clock paths
???Timing-dependent analysis
???Mode conflict checking

For the best clock tree synthesis with short clock insertion delay and low clock power, a platform for clock analysis as well as constraints verification and generation is crucial. ClockExplorer offers a platform that analyses and generates a visual clock structure and allows a design team to generate constraints for a CTS tool. These constraints from ClockExplorer result in an implementation that delivers short insertion delays and low clock power. It enables a front-end team to analyse clock structures and generate meaningful constraints for a CTS tool. The platform additionally allows a back-end team to do clock sign-in and optimisation of clock constraints for effective clock tree synthesis by a CTS tool.

About the author
Jason Xing is the Vice President of Engineering for ICScape Inc.

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