Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
EE Times-Asia > EDA/IP

Cadence's closure tool speeds chip designs to fabrication

Posted: 22 May 2013 ?? ?Print Version ?Bookmark and Share

Keywords:Cadence? timing analysis? SoC? fabrication?

Cadence Design Systems has recently unveiled the Tempus Timing Signoff Solution, a new static timing analysis and closure tool designed to enable System-on-Chip(SoC) developers to speed timing closure and move chip designs to fabrication quickly. The Tempus Timing Signoff Solution a new approach to timing signoff tools that enables customers to shrink timing signoff closure and analysis for faster tape-out while producing designs with less pessimism, area and power consumption.

The Tempus Timing Signoff Solution boasts a distributed timing engine which can scale to use up to hundreds of CPUs. Parallel architectures allow solution to analyse designs in the hundreds of millions of instances without compromising accuracy. It also boasts a path-based analysis engine that leverages multi-core processing to reduce pessimism. With its performance advantage, the solution enables broader use of path-based analysis. Cadance's latest solution also features multi-mode, multi-corner (MMMC) analysis and physically-aware timing closure.

"Today, the time spent in timing closure and signoff is approaching 40 per cent of the overall design implementation flow. Traditional signoff flows have failed to keep pace with the increasing demands of achieving timing closure on complex designs," said Anirudh Devgan, corporate vice president, Silicon Signoff and Verification, Silicon Realisation Group at Cadence.

The Tempus Timing Signoff Solution advanced capabilities can handle designs containing hundreds of millions of cell instances without compromising accuracy. Initial engagements with customers have shown that the Tempus Timing Signoff Solution can achieve timing closure in days on a design that would have taken several weeks with traditional flows.

"We are pleased to see new capabilities in the area of static timing analysis (STA) from Cadence," said Sanjive Agarwala, director of processor development, Texas Instruments. "As we move to more advanced process nodes, timing closure becomes more difficult. It's great to see Cadence taking on this challenge by offering new technology designed to tackle tough design closure issues."

Article Comments - Cadence's closure tool speeds chip d...
*? You can enter [0] more charecters.
*Verify code:


Visit Asia Webinars to learn about the latest in technology and get practical design tips.

Back to Top