Channel compensation methods in JESD204B converter

The new high speed serial interface for data converters, JESD204B standard, makes provisions for a maximum speed of 12.5Gbps. With high performance ADCs and DACs supporting several JESD204B lanes of data, the complexity of routing, maintaining signal integrity, minimising channel insertion loss attenuation, and compensating for inter-symbol interference (ISI) can create a challenge for system engineers to maintain JESD204B compliance in their application.

Many applications, such as those in the healthcare segment, have multiple sensors with signal acquisition that can be a significant distance from the data processing engine. Careful layout practices and board design guidelines can help reduce the need to expend time troubleshooting prototype system issues due to a high bit error rate (BER). In addition, converters with either the JESD204B receiver (DAC) or transmitter (ADC) can offer channel compensation strategies on their physical layer (PHY) capable of minimising the design effort and the time needed to successfully implement the new interface between ADCs, DACs, FPGAs, and ASICs at maximum speed.

JESD204B transmission system
In a typical JESD204B transmission interface, the board channel will act as a low pass filter transfer function in the system due to the capacitive effective of the PCB traces on the dielectric material of the board. Transmitter pre-emphasis and de-emphasis from an ADC or FPGA output, coupled with receiver equalisation (EQ) on a DAC or FPGA input can effectively boost the high frequency content for the total system as seen at the end receiver. If this is done correctly, the result is nearly a flat frequency response through the transmission system with a much lower risk of bit errors across the link. Ideally, all these methods can be modelled in one system simulation to predict the bit error performance over the link. The known properties of the channel such as PCB length, dielectric constant and differential impedance down the transmission line can be optimally modelled against the settings of the transmitter and receiver channel compensation.

Pre-emphasis
Within an ADC or FPGA, the JESD204B transmitter PHY compensation methods known as pre-emphasis and de-emphasis help achieve a near flat frequency response on the channel. Where a normal unaltered channel exhibits a frequency roll-off relative to the trace length and board materials, a channel using pre-emphasis provides high frequency boost and acts like a high pass filter to compensate for the loss as the signal is boosted in time over the nominal Vpp levels. Thus, the system response on the pre-emphasis channel is balanced due to the amplification of the high frequency content.

A channel using pre-emphasis has a larger signal peak to peak voltage (Vpp) on certain bit transitions than without pre-emphasis, causing a high frequency boost in the frequency domain. This allows data to be transmitted longer distances as the effects of the low frequency roll-off can be mitigated. In a high speed serial interface such as JESD204B, a processing technique called pre-emphasis can be used to amplify rise/fall times of high bandwidth portions of the data. In the analogue domain, this can be accomplished through a term known as "charge injection" that focuses additional charge at specific points in the data stream to boost high bandwidth signals.

Using a pre-emphasis technique, the original signal is passed through a high pass filter, fundamentally similar to a series capacitor for example, and then added back to the original signal. An example of this configuration can be seen below. It is critical that the high pass filter network is designed to enhance only a certain range of data rates that are of interest for the application, otherwise the technique will not be effective.