Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
EE Times-Asia > EDA/IP

Mentor teams up with OpSIS, Lumerical on PDK dev't

Posted: 29 May 2013 ?? ?Print Version ?Bookmark and Share

Keywords:PDK? silicon photonics process? IC design?

Mentor Graphics Corp. has teamed up with OpSIS and Lumerical Solutions to develop a complete EDA-style, full flow process design kit (PDK) for the OpSIS IME silicon photonics process. According to them, the prospect of integrating a silicon photonics process with silicon-based electronics would allow adding the driver and control electronics on the same chip, greatly reducing packaging complexity and cost. Adding a photonic layer and interconnects also holds the promise of solving speed bottlenecks in future computing and chip platforms, the firms added.

After almost a year of development and testing by the combined team of OpSIS, Mentor and Lumerical, the OpSIS team has demonstrated a prototype full design implementation and verification flow for the IME silicon photonics process. This flow uses the Mentor Pyxis custom IC design platform for schematic capture and schematic-driven layout, along with the Mentor Calibre nmDRC and Calibre nmLVS tools with detailed parameter checking for physical verification of the design. This prototype flow is available for design teams who participate in an OpSIS MultiProject Wafer design workshop.

The OpSIS PDK relies on technology from Lumerical Solutions for optical simulation that is set up to let users create and manage Lumerical INTERCONNECT projects inside the Pyxis environment. Lumerical INTERCONNECT is used to provide system level optical analysis of integrated silicon photonics circuits. Compact model development work is ongoing using Lumerical's FDTD Solutions, MODE Solutions and DEVICE to complement the experimental data.

Within the Pyxis custom IC design platform, the OpSIS PDK currently supports call-back driven photonic PCells that can be quickly assembled using connectivity-driven waveguide routing with radial and adiabatic bends, as well as S-bend support. Design rule checking is done with the Calibre nmDRC tool using out-of-the-box SVRF rules with special considerations for silicon photonic structures, along with the Calibre nmLVS tool for device checking that is similar to other high-volume design flows used in the industry. Tiling and mask preparation is done using Calibre SmartFill in conjunction with the Calibre DESIGNrev tool. Mentor has also partnered with OpSIS to ensure access to design tools so this does not become a barrier to the development of silicon photonics test chips.

Article Comments - Mentor teams up with OpSIS, Lumerica...
*? You can enter [0] more charecters.
*Verify code:


Visit Asia Webinars to learn about the latest in technology and get practical design tips.

Back to Top