Arm rolls out power optimised Cortex-A15 hard macro

Arm has recently unveiled a power-optimised dual-core hard macro implementation of the Arm Cortex-A15 processor. The implementation is touted to provide exceptional power efficiency and is capable of delivering up to 10,000 DMIPS within a constrained mobile power envelop.

Arm was able to achieve a hard macro development on the Cortex-A15 by using a combination of Arm Cortex processor IP, Artisan physical IP, CoreLink systems IP and the company's integration capabilities and uses TSMC's 28nm HPM process.

The complete low leakage implementation features integrated NEON SIMD technology and a virtual floating point engine, and includes a 1MB level 2 cache to deliver an extremely competitive balance of performance and power. It is ideal for a wide range of power-sensitive handheld devices such as mobile phones and tablets. This dual-core hard macro was implemented using ARM Artisan 9-track libraries and incorporates ARM POP Technology for the Cortex-A15 on TSMC's 28nm HPM process.

The Cortex-A15 processor delivers up to twice the performance of smartphones based on the Cortex-A9 processor. The dual-core hard macro accelerates time to market for semiconductor companies wanting to benefit from the most advanced processor technology available. This Cortex-A15 implementation is an ideal solution for designers of big.LITTLE processing systems as it can be paired with a dual- or quad-core Cortex-A7 processor, simplifying the design process and enabling a faster time to market.

This hard macro is ideal for designers looking for a cost-effective, highly power-efficient Cortex-A15 dual-core solution for mobile applications, and also devices such as single board computers that are used across a wide array of end-markets. It is an important addition to the ARM hard macro portfolio and will enable a wider array of partners seeking to leverage the outstanding capabilities of the Cortex-A15 processor.