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Parasitic extraction in the double-patterning age

Posted: 06 Jun 2013 ?? ?Print Version ?Bookmark and Share

Keywords:DRC? DFM? double-patterning? electrical sign-off? static timing analysis?

As major foundries announce the release of their 1.0 versions of 20 nm processes, we now see IC designers transitioning to production design and implementation of integrated circuits at this node. For many companies, test chips are complete, IP is developed, and process flows are defined. The challenge now shifts from characterisation, modelling, and other activities needed to define the feasibility of a new process node to actually taping out production chips on the new technology. For any new process, there are the customary concerns such as design complexity, electrical behaviour modelling, and the definition of new physical implementation and verification techniques that will deliver the most robust designs. Additionally, there are node-specific challenges driven by new manufacturing techniques that create new requirements for design rule checking (DRC), design for manufacturing (DFM), physical implementation, and parasitic extraction. At 20 nm, the node-specific challenge is double-patterning (DP), and physical implementation teams are wrestling with how to achieve timing and electrical sign-off under this new paradigm.

The need for DP at 20 nm has been well documented. To achieve better fidelity of 20 nm designs, we need to decompose individual layers into 2 separate masks and perform the lithography for a given layer in 2 distinct steps. This technology will evolve to triple patterning and multi-patterning at newer nodes, and is the catalyst for new techniques in design and verification tools. Now, as we move towards production tape-outs at 20 nm, questions arise regarding the electrical implications of DP. With layers being decomposed into different masks, will there be new sources of variation? If so, how do we account for that variation, and what impact will that have for static timing analysis (STA), signal integration (SI), and power analysis (PA)? And, if there are new requirements, how can they be addressed without increasing the time spent in the tape-out analysis flow? Parasitic Extraction (PEX) represents the input to electrical analysis flows, so determining the impact of DP on electrical sign-off can be better achieved by understanding how PEX tools have evolved to handle this challenge.

There are two main innovations for PEX tools that address DP:

???Modelling to account for variation due to mask misalignment
???More efficient processing to maintain reasonable cycle time for electrical sign-off

Figure 1: Mask shifts will affect capacitance modelling.

Modelling for mask misalignmentWith DP, there will be additional sources of variation. The light and dark blue lines in Figure 1 depict metal wires on the same layer, but the different colours indicate that they reside on different masks. During lithography, these masks may not be perfectly aligned, and any misalignment in the x, y, or z direction will have an impact on parasitic capacitance calculation. The red regions indicate where coupling capacitances increase, and the orange regions are an indication of decreased coupling capacitances, due to mask shifts. Compared to perfectly aligned masks, a 2 nm offset could have a 5% impact on coupling capacitance values, while a 6 nm shift could result in differences as high as 20%. The challenge is to quantify the mask shifts appropriately, and incorporate that shift into the capacitance calculation.

IC manufacturers have worked very hard to quantify the amount DP masks will shift, and are working just as hard to keep that shift to a 1-2 nm delta. Using foundry data, PEX tools have developed corner methodologies to account for the differences between typical alignment, as well as shifts in the x, y, and z directions. As with traditional interconnect corners, DP corners are used to place bounds on the amount of capacitance variation that will be seen, which means if a design passes sign-off requirements across the range of DP corners, then the manufactured silicon will be robust against process differences and still perform to specification.

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