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Parasitic extraction in the double-patterning age

Posted: 06 Jun 2013 ?? ?Print Version ?Bookmark and Share

Keywords:DRC? DFM? double-patterning? electrical sign-off? static timing analysis?

Additionally, to prevent overly conservative results from parasitic extraction, PEX tools have evolved to incorporate "coloured" layout and to make colour assignments. Colouring is the process used by physical implementation and physical variation tools to assign different wires to different masks. This is a necessary function for implementation and verification tools because there are different DRC and DFM requirements based on the mask assignment for wires. For PEX, wires on the same mask will not have variation respective to each other, based on DP. It is the wires on different masks that need the additional computation. By incorporating coloured layout, PEX tools can apply the analysis only where it is necessary, and develop variation or corner models for the wires on different masks to accurately represent the variation that is possible across all corners of the design.

More efficient processingOne obvious implication of DP for PEX is more corners. In fact, there are now corners within corners. For each typical process corner, there can be as many as 3 DP corners. At 28 nm, most IC manufacturers were recommending 5 process corners (typical, C Best, C worst, RC best, and RC worst). At 20 nm, there can be as many as 15 corners (including DP), and most foundries are offering 11. Since designs are also growing in complexity at each successive node, a big challenge for PEX at 20 nm is processing the design and the necessary corners without incurring additional cycle time for the sign-off flow.

Traditionally, each corner means a full run of the PEX tool. Therefore, 5 corners requires 5X the runtime of a single corner, and 11 corners requires 11 times the runtime. Using traditional methods, the 20 nm designer would have to incur either 2X the runtime or 2X the hardware of a 28 nm design. A better solution is more efficient processing. Most of the computation time in PEX is spent processing the physical design. The design is the same as 28 nm, and the only difference between the various corners is the spacing or dimension of the wires. The variation from corner to corner is captured in either tables or equations, depending on the foundry or the PEX tool. Modern PEX tools can process all corners simultaneously to incur only minimal additional run time. Figure 2 shows a PEX tool that incurs 4% additional runtime per corner with no impact on accuracy, meaning 11 corners can be processed in less than 1.5X the runtime of a single corner. With this type of tool, complete corner processing can be achieved more quickly at 20 nm than with the use of a traditional tool at 28 nm.

Figure 2: Traditional corner processing vs. newer, more efficient methods.

Overall, DP has a profound impact on PEX and subsequent electrical analysis flows. However, with new modelling techniques and more efficient processing, the industry will improve sign-off methodologies without loss of accuracy or incurring additional turnaround time. As one of my colleagues likes to say, "Each new node is a dry run for the next run." If that's true, then these developments are fortuitous, since the next nodes will bring the challenges of triple patterning and FinFets.

About the author
Carey Robertson is a Director of Product Marketing at Mentor Graphics Corp., overseeing the marketing activities for Calibre PERC, LVS and extraction products. He has been with Mentor Graphics for 15 years in various product and technical marketing roles. Prior to Mentor Graphics, Carey was a design engineer at Digital Equipment Corp., working on microprocessor design. Carey holds a BS from Stanford University and an MS from UC Berkeley.

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