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TSMC certifies Mentor EDA tools for 16nm FinFET

Posted: 04 Jun 2013 ?? ?Print Version ?Bookmark and Share

Keywords:FinFET? SoC? verification? design?

Mentor Graphics has announced that its Calibre physical verification platform has passed initial design reference and SPICE modelling tool certification for TSMC's upcoming 16nm FinFET process node.

The EDA firm's Olympus-SoC place and route system, which enables efficient double patterning (DP) and timing closure with comprehensive support for new design rule checks and multi-patterning rules, fin grid alignment for standard cells and macros during placement, and Vt min-area rule and implant layer support during placement, also achieved certification from TSMC.

The Calibre nmPlatform product for 16nm FinFET supports advanced design rule definition and litho hotspot pre-filtering. In addition, the Calibre SmartFill facility was enhanced to support the TSMC-specified filling requirements for FinFET transistors, including support for density constraints and multi-layer structures needed for FinFET layers. The SmartFill solution also provides double patterning support for back end layers and user-defined fill cells that are automatically inserted into a layout based on analysis of the design.

Reliability is also a key element of TSMC's 16nm FinFET process technology. FinFET 3D transistors will enable devices with higher drive strengths than at previous nodes, so accurate reliability verification becomes even more critical. As highlighted in the Design Enablement section of the recent TSMC Technology Symposium, reliability checks based upon the Calibre PERC platform will enable customers to analyse and correct issues like electrostatic discharge and latch-up.

In related news, Mentor and TSMC also announced that they will expand their 20nm IC physical verification offering. The continued collaboration between the two firms has reduced Calibre nmDRC 20nm signoff runtimes by at least a factor of 3x and memory requirements by 60 per cent compared to initial design kits released last year. In addition, Calibre PERC N20 design kits are now available to TSMC customers as part of the companies' ongoing collaboration for IC reliability improvement. The partnership will continue as mutual customers ramp their releases of N20 production designs, with the goal of maintaining rapid turnaround on full-chip signoff runs for the largest SoC designs in the industry.

The Calibre PERC kit for N20 includes new checks for latch-up prevention and IO-ESD protection, and a number of multiple power domain checks, which represent a significant step forward in automating procedures that previously had to be done manually. Moreover, by using both the Calibre PERC and Calibre nmDRC kits, customers are able to quickly identify and correct voltage-aware DRC violations, which is critical for today's multi-voltage advanced process designs.

Other ongoing collaboration between TSMC and Mentor is focusing on optimising the Calibre DFM product family, which incorporates TSMC's unified DFM (UDFM) engine. Improvements are expected to result in runtime reduction in TSMC's latest DDK release, and customers who use any DFM tools compliant with TSMC UDFM engine will benefit.

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