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Example of LPC24XX external memory bus

Posted: 13 Jun 2013 ?? ?Print Version ?Bookmark and Share

Keywords:LPC24XX? asynchronous? dynamic memory? PCB? bus?

The LPC24XX provides multiple static and dynamic memory chip select outputs to enable designers to work with a large set of memory topologies. Designers must take care to ensure that their PCB satisfies the electrical and timing characteristics of the external memory bus or their embedded systems may not be able to operate reliably at maximum frequency.

The ability of a memory bus with multiple devices to operate properly is dependent on several factors: the electrical characteristics of the memory devices, the operating frequency of memory transactions, the length of the traces between the LPC24XX and memory device, as well as the voltage levels being used.

This document will detail an example design illustrating how to connect asynchronous and dynamic memory elements to the external memory bus of the LPC24XX. This note also includes a set of suggested design rules which apply to both the schematic capture and layout phases of PCB design.

View the PDF document for more information.

Originally published by NXP Semiconductors at www.nxp.com as "LPC24XX external memory bus example".





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