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Address jitter, noise with DDR4 (Part 2)

Posted: 11 Jun 2013 ?? ?Print Version ?Bookmark and Share

Keywords:JEDEC? DRAM? DDR4? Vcent? jitter?

In part 1 of this feature on the new JEDEC DRAM specification, DDR4 (JESD79-4), we discussed how noise and jitter can be significant problems at high speeds and how DDR4 applies communications-industry techniques to solve the problem. In this second part, he will discuss specifics such as the DDR4 eye mask and how it can be used to improve designs.

The DDR4 mask consists of concentric white and blue rings inside a drawing of typical DDR4 data eye as it might be measured on an oscilloscope or logic analyser. The inner part of the mask, labelled deterministic, shows the part of the DRAM mask that is due to deterministic noise and timing behaviour within the DRAM. This part of the mask is constant. The outer part of the mask shows the part of the DRAM behaviour that is due to random voltage and timing effects within the DRAM. The thickness of this ring as given in the JESD79-4 specification itself corresponds to the total random jitter and noise effects at a BER of 10-16.

Random jitter and noise effects are assumed to have a Gaussian distribution. This is the same assumption made in the dual-Dirac model used by most high-speed serial specifications. The DRAM parameters for the width of the data valid window (tdiVW_total) and the height (VdiVW_total) given in the DDR4 spec are the sum of the random and deterministic parts of the mask at an error rate of 10-16. These two parameters alone define the total size of the DRAM's receiver data-valid window. For the first time, to support the higher speed clocks required by DDR4, the DDR4 clock parameter specification defines deterministic and random components. This helps when Defining DRAM data and clock behaviour this way allows the actual behaviour of real devices to be described without the burden of adding extra margin just to satisfy the old assumptions of "perfect" data transfer. An additional benefit is the elimination of the need for slew-rate de-rating, removing one of the most troublesome parts of the DRAM spec.

Where this mask is placed is, of course, just as important as the size of the mask. In DDR4, the mask centre is placed where the differential DQS strobe crosses 0 V. Normally, you might expect the mask to be placed at the middle of the data eye (50% of the Unit Interval or 1/(2 * *data transfer rate). This is usually not where the eye is most open, however. During write training, the controller and DRAM communicate to discover the optimal placement of the DQS strobe to minimise the error rate. By placing the DRAM mask where the DQS signal is observed to cross 0 V the actual results of write training can be used in measuring the data eye. This makes sense because that is when the DRAM samples the data.

Vertical placement of the DRAM mask using Vcent
The vertical placement of the DRAM mask is determined by a new parameter called Vcent. Vcent is similar to the traditional Vref parameter but takes into account the fact that the actual reference voltage used inside the DRAM is adjusted during write training and is not physically visible at the balls of the DRAM.

At the high speeds specified for DDR4, the actual centre of the data eye provided to the DRAM may shift up and down slightly from one device to another. This could be due to variances in PCB layout, power distribution SSO or other effects. During initialisation of the DDR4 bus, the controller communicates with the DRAM to discover the optimal Vref setting for each DRAM to minimise the error rate. This can differ from device to device. Although it would be ideal to measure the DRAM mask at the optimal Vref for each DRAM, this is impractical. Not only would a ball need to be assigned to output the internal Vref, this signal would need to be probed on each DRAM. This would mean accessing Vref on dozens of DRAMS. Even if Vref was probed, bringing the signal to off-chip would cost power or would risk introducing noise on the Vref signal, reducing reliability.

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