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Maxim CEO talks analogue, strategic integration

Posted: 07 Jun 2013 ?? ?Print Version ?Bookmark and Share

Keywords:analogue? design? foundry?

The first generation of analogue products made in a sub-100nm analogue process technology is about to debut from Maxim Integrated, an enabler for its integration strategy. In a wide-ranging interview, Maxim Integrated chief executive Tun? Doluca talks about the new process, gives an update on his strategy and shares thoughts on Intel, Samsung and China.

Analogue designs don't benefit from finer process technologiesin fact they become more problematic. Thus many designs are still made in 250 and 350 nm processes.

Maxim's current "workhorse" is its 180nm process with support for 70-80V transistors, said Doluca. The same is roughly true for analogue giant Texas Instruments and others such as On Semiconductor, said Stephan Ohr, analogue analyst at Gartner Inc.

Maxim aims to differentiate itself by building application-specific, integrated analogue and digital parts in addition to the standard analogue building blocks made by competitors such as TI and Linear. The new Maxim process appears to be motivated by both types of designs.

Analyst Ohr speculates Maxim's new process could use thinner vertical cell structures to reduce die area. Alternatively, it might be a planar process that doesn't require more area to support higher current, he said.

Doluca on Maxim's new process

Tun? Doluca: We're working on the next node, probably in the 90nm range. The process development is internal, but we will partner for capacity.

Foundry partners for the process will most likely be someone different [from current partners lead by 300mm wafer supplier Powerchip that makes about a third of Maxim's products]. Part of our strategy is to build chips on 300mm wafers because the parts are used in mobile products, and they need the high capacity and low cost structure of 300mm wafers.

The new process has new requirements, so you have to see who has the right fab to build it. We want to leverage what others have. With chip capacity from our current foundry partners, we already could do $4 billion in sales and we are at $2.5 billion in revenue, so we have room.

The new process will support high voltage designs and far denser digital designs. It's still a bipolar CMOS/DMOS technology, but with finer geometry and some new things on the analogue front.

MEMS manufacturing is still a separate process resulting in a component integrated at the package, not the die level.

We probably will ship the first parts designed in the new process next year. We are designing in it right now, but it will take time to qualify the process.

EE Times: Who else is working on sub-100nm analogue processes?

Doluca: I imagine the suppliers focused on mobility are probably working on it but everyone is very secretive. So we don't know exactly but I imagine TI and Qualcomm and Dialog. We keep our technology development close to the chest, too, because it's a differentiator.

A call to action for EDA

EE Times: What's the latest on your integration strategy?

Doluca: We put a lot of energy into this for five years, and there have been a lot of growing pains. In the mid-2000's they made up a low teens percentage of our sales. Today they exceed 40 per cent of sales. We are evolving our design methodologies. Different groups advance at different rates. Organisations with roots in the digital side have done this change more rapidly.

Our smart meter products, for example, were designed by microcontroller guys who added analogue so their flow is right. More conventional groups are taking longer. It's a major initiative this year to make sure we are all on the same page.

It's not that easy. You need a complete change in mindset to be more market oriented, and the tools are not as advanced as they are in digital.

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