Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
EE Times-Asia > Memory/Storage

DRAM makers find new processes for sub-nm DRAM cells

Posted: 12 Jun 2013 ?? ?Print Version ?Bookmark and Share

Keywords:DRAM? SDRAM? cell array? storage capacitor?

Analysis of leading-edge DRAM cell technologies currently used reveal that major DRAM manufacturers will keep going to 2x-nm or even 1x-nm technology nodes even though some forecasts predict that DRAM memory cells would hit a scaling wall at 30nm.

TechInsights recently analysed process and device architectures of mass-produced 3xnm SDRAM cell array structures from major manufacturers including Samsung, SK-Hynix, Micron/Nanya and Elpida and concluded the technologies can be scaled further. The consensus approach incorporates buried wordlines (b-WL) and fin-shaped access transistors.

At the current low-3x-nm technology node on the DRAM cell architecture timeline, the most important factors in process integration are how to effectively increase channel length of access MOSFETs and how to scale down the storage capacitor area in DRAM cell arrays.

Buried metal wordlines with a saddle shaped (or bulky fin-type) channel configuration is a key solution to drive the direction of 3x/2x nm access transistor scaling, having well-controlled threshold voltage and ultra-low leakage current. The larger channel width and length the device has, the better immunity to short channel effects and higher on-current we have. Four manufacturers use a similar process flow for the recess and fin-type transistor.

The fin shape of each transistor is shown in Figure 1. Micron and SK-Hynix use a bulky fin-shape like a trapezoid. According to an estimation of the integrated channel width and channel length, the Micron/Nanya cell transistor has the largest channel width and the Elpida cell transistor has the largest channel length among the four devices. Referring to b-WL gate materials, Samsung adopted a TiN metal gate with higher resistance than tungsten, which is different from other three manufacturers. For bitline stacks, all the devices use a tungsten (W) based material. However, the barrier materials between tungsten layer and poly-Si layer are different from each other.

3D bulky FinFET comparison

Figure 1: Comparison of 3D bulky FinFET channel structure in the wordline direction. All the manufacturers use similar process integration for b-WL structures. Different fin-shape are adopted for each device width.

1???2???3?Next Page?Last Page

Article Comments - DRAM makers find new processes for s...
*? You can enter [0] more charecters.
*Verify code:


Visit Asia Webinars to learn about the latest in technology and get practical design tips.

Back to Top