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DesignWare HPC Kit expanded for core optimisation

Posted: 14 Jun 2013 ?? ?Print Version ?Bookmark and Share

Keywords:Synopsys? embedded memory? logic library? IP?

Synopsys recently announced an extention to its DesignWare duet embedded memory and logic library IP portfolio, which is designed to enable the optimised implementation of a broad range of processor cores. The new DesignWare HPC (High Performance Core) design kit contains a suite of high-speed and high-density memory instances and standard cell libraries that allow system on chip (SoC) designers to optimise their on-chip CPU, GPU and DSP IP cores for maximum speed, smallest area or lowest power or to achieve an optimum balance of the three for their specific application.

"Our work with Synopsys has resulted in significant improvements in the area and energy efficiency implementations of our IP cores utilising Synopsys' memories and standard cell libraries," said Mark Dunn, executive vice-president of IMGworks SoC Design at Imagination Technologies. "Our most recent project was building a PowerVR Series6 GPU core using cells and memories from Synopsys' HPC Design Kit. We achieved an overall reduction of 25 per cent in dynamic power as well as a 10 per cent area savings, with some blocks achieving a 14 per cent area improvement. We also created a tuned design flow that has delivered a 30 per cent improvement in implementation turnaround time."

Synopsys' broad portfolio of DesignWare IP includes silicon-proven embedded memory compilers and standard cell libraries that support a range of foundries and processes from 180nm to 28nm and have shipped in more than three billion chips. The DesignWare Duet Package of Embedded Memories and Logic Libraries contains all the physical IP elements needed to implement a complete SoC including standard cells, SRAM compilers, register files, ROMs, datapath libraries and Power Optimisation Kits (POKs). Options for overdrive/low- voltage process, voltage and temperature (PVT) corners, multi-channel cells, and memory built-in self-test (BIST) are also available. The DesignWare HPC Design Kit adds performance, power and area optimised standard cells and memory instances tuned for the special speed and density requirements of advanced CPU, GPU and DSP cores.

The HPC Design Kit contains fast cache memory instances and performance-tuned flip-flops that enable speed improvement of up to 10 per cent over the standard Duet package. To minimise dynamic and leakage power as well as die area, the new kit provides area-optimised and multi-bit flip-flops and an ultra-high-density two-port SRAM, delivering demonstrated reductions in area and power of up to 25 per cent while maintaining processor performance.

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