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Imec presents RRAM, FinFET innovations

Posted: 14 Jun 2013 ?? ?Print Version ?Bookmark and Share

Keywords:RRAM? FinFETs? RTN? NMOS?

Imec took the stage at this week's VLSI 2013 Technology Symposium held in Kyoto, Japan to showcase its progress in increasing the understanding of the stochastic nature of Resistive Random Access Memory (RRAM) operation as well as new insights into 3D field effect transistors (FinFETs).

Current (Flash) memory technologies are believed to face scaling limitations down to the 15-16nm technology node. One of today's most promising concepts for scaled memory is RRAM which is based on the electronic (current-or voltage-induced) switching of a resistor element material between two metal oxides. Imec's research efforts on RRAM tackle scalability, low-voltage/low-current operation, as well as understanding the operation mechanisms and reliability optimisation of this memory concept. Researchers presented an improved quantitative statistical prediction of the RRAM operation by adding a stochastic component in their previously described Hourglass concept, a model that facilitates RRAM cell design. The optimised model is used to suggest engineering guidelines for stable operations in filamentary RRAM.

One of the critical reliability parameters impacting the memory state during read operation in resistive memory is Random Telegraph Noise (RTN). Imec presented a study showing impact of filament configuration on the RTN signal. This analysis helped in proposing guidelines to engineer the dielectric for reduced RTN effects in low operating power.

Imec also presented at the VLSI 2013 Symposium the first strained germanium devices based on a Si-replacement process, where a Ge/SiGe quantum-well heterostructure is grown by epitaxially replacing a conventional Si-based shallow trench isolation (STI). The technique allows for highly-versatile means of heterogeneous material integration with Si, ultimately leading the way to future heterogeneous FinFET/nanowire devices. The device shows dramatically superior gate reliability (NBTI) over Si channel devices due to a unique energy band structure of the compressively-strained Ge channel.

According to Aaron Thean, logic devices programme director at Imec: "We are facing significant challenges to scale the MOSFET architecture towards 7nm and 5nm. Besides dimension scaling, enhancing the device performance, in the face of rising parasitics and power, is a major focus of the logic device research at Imec. Among the key activities are R&D efforts investigating both high-mobility channel material and new methods of enhancing Si-based FinFET."

With options to introduce heterostructure into next-generation FinFET, quantum-well channels based on a combination of materials that enhance both mobility and electrostatics, can be engineered. Researchers also presented comprehensive simulation work that investigated material combinations of Si, SiGe, Ge and III-V channels to enhance device electrostatics, providing important process guidance to extend FinFET scalability.

Moreover, Imec presented novel highly scalable engineering approaches to tune gate workfunction and improve mobility, noise and reliability in Si NMOS FinFETs. The impact on the performance of layout-induced stress effects in scaled FinFETs and the impact of random telegraph noise (RTN) fluctuation in lowly doped devices was shown.





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