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Processors feature Imagination's MIPSr5 architecture

Posted: 19 Jun 2013 ?? ?Print Version ?Bookmark and Share

Keywords:MIPS? IP cores? network processing?

Imagination Technologies has revealed that Cavium Inc. has licensed and incorporated the latest Release 5 MIPS architecture (MIPSr5) features, including hardware virtualisation, in all members of its ultra-high-performance 1-48 core OCTEON III family of products. The processors claim to deliver more than 100Gb/s of application performance per chip, and provide among the highest compute power of any standards-based communications processor chip with 120GHz of 64bit compute processing per chip.

Imagination's family of MIPS processors are geared for products where ultra low-power, compact silicon area and a high level of integration are required. MIPS processor IP cores and architectures range from ultra-low power 32bit MCUs to scalable 32bit and 64bit multi-core solutions for advanced application and network processing platforms.

According to Imagination, its MIPS architecture is the industry's most efficient RISC architecture, delivering the best performance and lowest power consumption in a given silicon area. SoC designers can use this efficiency advantage for significant cost and power savings, or to implement additional cores to deliver a performance advantage in the same power, thermal and area budget.

The seamlessly compatible MIPS32 and MIPS64 instruction-set architectures (ISAs) allow customers to port from one generation to the next while fully preserving their investment in existing software. MIPSr5 architecture incorporates important functionality including hardware virtualisation and Single Instruction Multiple Data (SIMD) modules.





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