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Designing highly reliable FPGA designs

Posted: 26 Jun 2013 ?? ?Print Version ?Bookmark and Share

Keywords:single event upset? SEU? FPGAs? Finite State Machine? FSM?

Radiation-induced soft errors called "glitches" became widely known in the 1970s with the introduction of dynamic RAM chips. The problem emerged as a result of radioactive contaminants in chip packaging, which emit alpha particles as they decay and subsequently disturb electrons in the semiconductor. This disturbance can result in an unwelcome change in voltage levels in digital logic.

In combinational logic, the voltage disturbance will most likely be transient; an unwanted transient signal is known as a single event transient (SET). However, synchronous logic C such as state machines, registers and memory C can store and propagate the transient error, which is likely to result in hardware failure. Such a stored error is known as a single event upset (SEU).

Figure 1: Single event upset (SEU) results from storing an unwanted transient event.

As far back as 1996, researchers at IBM estimated that each 256MB of RAM suffers one error per month as a result of soft errors. The error rate grows as logic densities increase, switching voltage levels decrease and switching speeds rise. Today's bigger, faster FPGAs will suffer from higher soft-error rates.

Beyond aerospace and defence applications
Indeed, soft errors still occur today as a result of radiation from space C even within electronic equipment operating at sea level. For many years, design teams working in aerospace and defence have been aware of the need to protect their designs against SEUs. Today, engineers working in other market sectors are adopting techniques to guard against SEUs. We are increasingly dependent on the safe operation in automotive systems and medical equipment, but high reliability is no longer purely a safety-critical issue; it is a growing concern even for networking and industrial automation systems that demand high quality-of-service and uptime.

Detecting and protecting against SEUs
For some applications, design teams choose to use radiation hardened ("rad-hard") devices that are physically resistant to soft errors. However, rad-hard devices such as MicroSemi's RT ProASIC 3 and Xilinx's Virtex-5-QVR FPGAs come at a price premium and, as a consequence, find use mainly in mission-critical space projects.

Fortunately, there are design-based techniques that engineers can use to detect and protect against soft errors in normal sequential logic FPGA structures. Synopsys' Synplify Premier enables design teams to automatically apply techniques that build safety into the design. These techniques include triple modular redundancy (TMR) and fault-tolerant Finite State Machine (FSM) implementation.

Safe finite state machines
A flipped bit in a state machine's state register can put the FSM into what the design team assumed would be an "unreachable" state under normal circumstances. The FSM can become stuck in the invalid state, which is potentially disastrous in, for example, a control logic module.

Safe FSM implementation involves using error-detection circuitry to force a state machine into a reset state or into a user-defined error state so the error can be handled in a specific way. The Synplify synthesis software can be instructed to automatically add error detection circuitry to identify errors and create additional error mitigation circuitry to return the FSM into a safe state, so that the chip resumes correct operation.

Figure 2: Additional error detection and mitigation circuitry is created to ensure correct FSM operation in the event of radiation-induced soft errors (SEUs).

For state machines that use "1-hot" state encoding, the error detection circuitry could be a parity checker, which ensures only one state register bit is high at any time. Once an error is detected, the state machine is then returned to a "safe" or "reset" state.

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