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Imec creates dielectric to scale NAND flash below 20nm

Posted: 25 Jun 2013 ?? ?Print Version ?Bookmark and Share

Keywords:Imec? NAND Flash? memory? 20nm?

A nano-scale hafnium aluminium oxide dielectric (HfAIO/AI203/HfAIO) stack has been created by researchers from Imec. The team of researchers will use the stack as an inter-gate dielectric with a silicon/titanium-nitride hybrid floating gate in a planar NAND Flash structure.

Imec said the three-layer structure that is high-k/low-k/high-k provides "excellent retention and endurance" of data. Imec did not quantify this but endurance of 105 cycles is considered a practical lower limit for NAND memory. Retention of 10 years is the standard in most shipping non-volatile memories.

NAND flash memory has migrated to a planar structure at around 20nm. The tightness of the memory cell pitch makes this necessary to avoid the wrapping the control gate round the floating gate. However, the planar cell therefore also demonstrates reduced coupling between control and floating gates making programming and reading harder.

The three-layer inter-gate dielectric has allowed an opening up of the program/erase window up to 18V. The dielectric is scalable in thickness making the material promising for further scaling of 2D NAND flash memory below 20nm, Imec said.

Using a 25nm thick stack (10-5-10) with an amorphous Al2O3 middle layer Imec produced a large improvement over single Al2O3 dielectric layer. Retention tests showed little loss of charge at temperatures of 125C.


Figure: Transmission electron microscopy pictures of the gate stack featuring a HfAlO/Al2O3/HfAlO inter-gate dielectric between the thin TiN from the hybrid floating gate and the TiN from the control gate. Source: Imec.

- Peter Clarke
??EE Times

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