Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
EE Times-Asia > Memory/Storage

The outlook for charge-trapping flash memory

Posted: 03 Jul 2013 ?? ?Print Version ?Bookmark and Share

Keywords:MirrorBit? charge-trap? NOR flash? Floating-gate? NAND?

For several technology generations, charge-trap flash memory has been successfully productized in high volume. Two-bits-per-cell MirrorBit charge-trap technology has been the industry benchmark for NOR flash for more than a decade, spanning six generations of scaling. More recently heterogeneous charge trap (HCT) NAND flash as well as embedded charge trap (eCT)NOR flash have been developed. The planar cell structures will enable continued scaling of these charge-trap technologies, while new architectures such as 3-D charge-trap flash will emerge and further extend the density-growth trend.

Floating-gate (FG) cells were utilised when the flash memory industry emerged in the 1980s. While FG cells are still commonly found today, the charge-trap flash has been scaling effectively, and has captured a significant portion of the market that requires high intrinsic reliability, small cell size, and good performance at elevated temperatures. Two-bits-per-cell MirrorBit flash is now ubiquitous in high-density parallel and serial NOR applications. 45-nm MirrorBit technology is in volume production today with 8-Gb chip, which is the highest-density monolithic NOR flash in the market (figure 1). Meanwhile, 32-nm MirrorBit cell has been demonstrated and will enable even higher density of monolithic NOR flash . For NAND applications, industry's first manufacturing-ready, charge-trap NAND technology called HCT NAND flash has been developed.

Figure 1: Die photo of 45-nm 8-Gb MirrorBit NOR flash product.

For SoC products with ultra-fast read access time, eCT flash is being integrated with an advanced logic process. In this paper, technological advancements and key attributes of each of these charge-trap technologies are presented.

MirrorBit NOR Flash
Spansion has been successfully scaling MirrorBit NOR flash for over ten years, with 32-nm development currently in progress (figure 2). With its virtual-ground architecture, MirrorBit technology is relatively immune to the gate-to-drain shorts and single-bit charge loss/gain seen in FG NOR technologies [1]. Key features of MirrorBit technology include buried bitlines, dual-poly memory gate, salicided wordlines, and design architecture optimised for fast access time and program speed. Charges are stored in localized regions of the non-conductive, charge-trap film near each of the two junctions, thereby providing two-bits-per-cell operation.

Figure 2: Scaling trend of MirrorBit and floating-gate NOR cells.

1???2???3???4?Next Page?Last Page

Article Comments - The outlook for charge-trapping flas...
*? You can enter [0] more charecters.
*Verify code:


Visit Asia Webinars to learn about the latest in technology and get practical design tips.

Back to Top