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The outlook for charge-trapping flash memory

Posted: 03 Jul 2013 ?? ?Print Version ?Bookmark and Share

Keywords:MirrorBit? charge-trap? NOR flash? Floating-gate? NAND?

HCT NAND is also capable of MLC operations. Good read window is maintained between adjacent Vt distributions past 15 K cycles, which is more than the typical endurance offered by FG MLC NAND at similar technology node.

Embedded charge-trap flash
MirrorBit NOR and HCT NAND architectures, as described above, are well suited for high-density applications. For embedded Flash applications in which the overall SoC performance is the predominant requirement, different types of cells have been proposed in the industry [7, 8]. To address this market, Spansion has the high-performance and scalable, embedded charge-trap (eCT) flash. MirrorBit cell is used as the foundation for eCCT, taking advantage of the highly reliable cell proven in volume production. Paired to the memory gate of eCT cell is a low-voltage select gate (figure 14). This cell configuration, along with the array-architecture optimisation, enables ultra-fast read and enhanced program and erase performance. With the random access time on the order of 5 to 10 ns, eCT Flash is ideal for high-end microcontrollers and other demanding SoC applications. With that in mind, eCT Flash is being integrated with an advanced logic process to deliver leading-edge SoC performance and low power consumption at the 40-nm node.

Figure 14: eCT cell architecture. Each cell is comprised of a charge-trap memory gate paired with a low-voltage select gate.

Through process, device, and design advancements, charge-trap technologies has been successfully productized in Flash memory. In respective applications, MirrorBit NOR flash, HCT NAND flash, and eCT flash are engineered to provide competitive attributes, such as bit size, density, performance, and reliability. These various flavours of charge-trap technologies also benefit from the improved scalability that planar cell structures inherently enable. Going forward, new architectures such as 3D Flash are inevitable extensions of the proven, charge-trap family of flash memory technologies.

Note: This work was first presented at the 2013 International Memory Workshop and appears here courtesy of the IEEE.

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7. B. Chen, International Symposium on VLSI-TSA (2007).
8. T. Kono et al., ISSCC, (2013).

About the author
Dr. Saied Tehrani is chief technology officer at Spansion, responsible for technology development, strategy, and new products. He has held leadership positions at Motorola, Freescale, and Everspin prior to joining Spansion in 2010. His work has been recognised with more than 75 U.S. patents; more than 70 co-authored articles in technical journals; and many awards, including the IEEE Daniel Noble award.

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