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Why oversample when undersampling is just right?

Posted: 12 Jul 2013 ?? ?Print Version ?Bookmark and Share

Keywords:ADC? sampling frequency? Oversampling? FPGA? high speed data?

System designers typically tend to employ ADC sampling frequency as twice the input signal frequency. As an example, for a signal with 70MHz input signal frequency with 20MHz signal bandwidth, system designers often use more than 140 MSPS sampling rate for ADC even though anything above 40 MSPS is sufficient as the sampling rate. Oversampling unnecessarily increases the ADC output data rate and creates setup and hold-time issues, increases power consumption, increases ADC cost and also FPGA cost, as it has to capture high speed data.

This application note describes oversampling and undersampling techniques, analyses the disadvantages of oversampling and provides the key design considerations for achieving the required ADC dynamic performance working with undersampling.

View the PDF document for more information.

Originally published by Texas Instruments at www.ti.com as "Why Oversample when Undersampling can do the Job?".





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