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SyncE timing chips boast phase jitter below 300fs RMS

Posted: 08 Jul 2013 ?? ?Print Version ?Bookmark and Share

Keywords:Integrated Device Technology? timing solutions? Ethernet? PHY? switches?

Integrated Device Technology recently unveiled its jitter ITU-T G.8262-compliant Synchronous Ethernet (SyncE) timing solutions. The new IDT 82V3910 is the a carrier-class SyncE-compliant phase-locked loop (PLL) device capable of meeting 10G or 40G Ethernet PHY jitter performance requirements. With phase jitter below 300fs RMS over the 10kHz to 20MHz integration range (with all channels in operation), the single-chip device offers 50 per cent less jitter than competing solutions and replaces multi-chip alternatives to reduce design complexity and cost.

The IDT 82V3910 and 82V3911 are low-jitter, highly-versatile SyncE network timing solutions optimised for use in 10GBASE-R/10GBASE-W and 40GBASE-R applications, including switches, routers, multi-service switching platforms, wireless backhaul equipment and other communications infrastructure. The innovative high-integration architecture includes two independent digital PLLs (DPLLs) to allow bidirectional synchronisation for maximum utility and simplified deployment. The DPLLs lock to a wide variety of telecom and Ethernet reference frequencies and suppress incoming timing faults to generate highly-reliable output clocks for optimal network performance.

The IDT 82V3910 SyncE SETS simplifies the timing circuit and bill-of-materials (BOM) by providing the synchronous equipment timing source (SETS) function to manage all required synchronisation timing signals. Ultra-low jitter generation makes the 82V3910 particularly suitable for single-board systems where the SETS directly times 10G or 40G network PHYs. The 82V3910 complies with ITU-T G.8262 for EEC-Options 1 and 2; and G.813 for SEC-Options 1 and 2; and is suitable for SyncE, SONET and SDH equipment. The 82V3910 can synchronise directly to a one pulse per second (1 PPS) reference enabling the host system to use a low-cost GPS receiver.

The single-chip 82V3911 SyncE PLL is pre-engineered to select references from a variety of SETS or network sources, perform clock rate conversions, and attenuate jitter C all while preserving the G.8262 compliance of the selected references. Furthermore, the 82V3911 reduces timing circuit BOM cost and board space by providing two PLL channels in a single chip.

The IDT 82V3910 and 82V3911 are available now and are encapsulated in a 196-ball 15x15mm CABGA Package.





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