Hypres commercially debuts new chip fabrication process

HYPRES Inc. recently publicized the launch of its newest six-layer planarized chip fabrication process. This new process increases the integration level of superconducting ICs and critical current density of Josephson junctions, making it ideal for customers developing high performance, energy efficient solutions for high-end computing, advanced wireless communications and instrumentation.

The six-layer fabrication process features new processes and techniques included in provisional patent application Rapid Integrated Planarized Process for Layer Extension (RIPPLE). This optimised process was offered to customers after the completion and thorough evaluation of several internal design iterations and successful production of working circuits.

"Our new fabrication process is rapid—approximately 20 per cent faster per layer—and is easily integrated with our current device designs by adding two new layers under the ground plane," explained Daniel Yohannes, Ph.D., Director of Fabrication Operations at HYPRES. "It is performed with one chemical mechanical polishing planarisation step per layer. Moreover, the process is extensible beyond the current six layers, paving the way for a soon-to-be-announced five-year, multi-layer roadmap the company will pursue."

Dr. Yohannes explained that the new process is implemented on its Canon 5X reduction stepper capable of supporting 250nm resolution limits. The new stepper process is very versatile and can be quickly tailored towards specific customer needs. "Special Runs" allow customers to order chips at their convenience, rather than timing orders to one of the foundry's regular mask schedules. In addition, the new process provides customers with increased purchasing value.

HYPRES' new fabrication process is open and available for broad commercial use. More information on the new process, the design tools, or to order chips can be found here.