Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
?
EE Times-Asia > Manufacturing/Packaging
?
?
Manufacturing/Packaging??

Saving embedded PCB design with forensic tech

Posted: 17 Jul 2013 ?? ?Print Version ?Bookmark and Share

Keywords:printed circuit boards? PCB? package-on-package? AOI? solder?

Ever shrinking printed circuit boards (PCBs) populated with greater numbers of package-on-package (PoP) devices have made it more challenging for design engineers to find causes of system failures. After spending many hours or days trying to uncover design defects and flaws using traditional methods such as automated optical inspection (AOI) or x-ray, design engineers may simply give up and discard their designs, losing the time and considerable money they've invested in them, simply because they cannot locate the culprit making their designs inoperable.

(AOI) or x-ray are highly reliable tools for conventional inspection but they aren't always able to detect elusive defects such as a micro hairline fracture within a solder joint, as shown in figure 1, or black pad or minute solder pin holes not seen at the 300 or 400 magnification level.

Figure 1: Micro hairline fracture within a solder joint.

Forensics to the rescue
Forensic technology may succeed where conventional inspection fails, in particular with advanced technologies like PoP. Board forensics using inspection kits consisting of scanning electron microscopes (SEM) and time domain reflectometry (TDR) are key sleuthing tools.

Figure 2 shows an impedance control chart with 90 ohms impedance shown on a TDR report with a 5 per cent tolerance.

Figure 2: 90 ohms impedance shown on a TDR report with 5% tolerance.

Forensic tools and techniques provide the microscopic detective work and uncover a variety of tiny design or manufacturing problems that automated optical inspection (AOI) or x-ray may miss.

Designing to avoid use of forensics
Embedded systems designers are faced with a myriad of new challenges posed by continually shrinking boards and advanced component packaging, like PoP.

One such area is 0.3 mm ultra-fine ball grid array (BGA) pitch design. In this case, as of this writing, there are no Association Connecting Electronics Industries IPC standards or guidelines for ultra-fine BGA pitch levels below 0.5 mm pitch. So, the savvy PCB designer pulls from his or her bag of tricks to perform the most efficient design possible.

Part of that is keeping in mind that land patterns are especially tight. The PCB designer knows that only one set of traces can go between the pads of these ultra-fine pitch BGA devices. But if two are used, manufacturing issues arise. Moreover, it's critical for the PCB designer to assure the fabrication house has the necessary leading-edge technology to deal with a high-caliber board that supports ultra-fine BGA pitch below 0.5 mm.

Stringent control of a design's transmit and return path is another key consideration. It should be as short as possible. The last thing the PCB designer wants is to create ripples in transmission and reception. Therefore, the tolerances of those impedance control traces should be extremely tightly matched. Tolerance should be within one to two per cent with a five per cent maximum. This creates a very clean eye diagram and keeps signal to noise ratios (SNRs) under control once the design is completed and undergoes simulation.

The PCB designer also has to take into account the fact that boards are not only getting smaller, but thinner. Earlier, the industry dealt with 62 mil thickness boards; now, providers are working with 47 and 31 mil and even thinner boards. The role the PCB designer plays in this case is to accurately define a panel size for small boards to assure optimal printing and placement.

1???2???3?Next Page?Last Page



Article Comments - Saving embedded PCB design with fore...
Comments:??
*? You can enter [0] more charecters.
*Verify code:
?
?
Webinars

Seminars

Visit Asia Webinars to learn about the latest in technology and get practical design tips.

?
?
Back to Top