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Address DRC debug issues in 20nm custom designs

Posted: 19 Jul 2013 ?? ?Print Version ?Bookmark and Share

Keywords:design rule checks? DRC? double patterning? verification? Calibre RealTime?

The number and complexity of design rule checks (DRC) have always grown over node, but as the semiconductor industry transitions to 20 nm and below, these increases are skyrocketing (figure 1). The traditional DRC verification flow used by custom layout designers simply can't provide the needed level of productivity when debugging DRC results at these advanced nodes. For example, custom layout designers are now confronted with complex checks that involve multiple factors, such as voltage-dependent design rule checks (VD-DRC) and double patterning (DP) checks.

In the long-established verification flow, the designer creates the layout in the design environment, writes out a GDSII file to disc, launches a DRC run, and then fixes the DRC errors in the design environment. Because the error correction and the validation of that correction are separate processes, designers must usually perform multiple iterations of this check-correct-verify process before they achieve signoff DRC closure.

Figure 1: The number and complexity of design rules has increased dramatically at 20 nm.

While this disconnect in the design flow has existed for many nodes, it did not create significant schedule delays at earlier nodes because error fixes were mostly straightforward geometrical adjustments of size and spacing. However, at 20 nm and below, the interactive nature of many of the new checks, and the limited area available in which to make adjustments, make debugging DRC errors a much more challenging and time-consuming process. Particularly in the case of DP, it can be extremely difficult to correct one error without creating another. As a result, the number of debugging iterations needed (and the time they require) to ensure a custom design is DRC-clean has been rapidly expanding, leading designers to sacrifice performance and yield to meet deadlines.

New debugging solutions are emerging that can help custom designers quickly and effectively achieve DRC closure on their advanced node designs. These new solutions provide a radical change to the traditional design flow. By integrating real time, signoff DRC feedback into the design environment, they help designers catch DRC errors early in the design cycle, and correct them within the design environment. Not only does this save valuable time in the design and verification cycle, but by checking designs against signoff DRC, designers can be confident that the corrections are DRC-compliant.

Let's take a look at how designers using these new solutions can check for DRC compliance, correct errors, and verify the changes within the design environment, creating a significant time savings while ensuring DRC-clean layouts. In our example, we'll use the Calibre RealTime integration with the Synopsys Laker OpenAccess (Laker) custom design environment to examine two checks from the 20 nm node that can be extremely difficult and time-consuming to check and correct using the traditional method.

Voltage-dependent design rule checks
When designing and verifying multi-input voltage designs, designers must ensure the layout complies with metal spacing design rules that are dependent on the voltage drop values on the signal nets. For example, a typical voltage drop rule might require that minimum spacing between metal lines must be x wherever the voltage difference between metal lines is higher than V (volt), otherwise the spacing must be y. The corresponding voltage drop check (VD-DRC) must ensure that these conditions are satisfied.

The inputs for our VD-DRC check are the maximum (MaxV) and minimum (MinV) voltage values on the nets. The DRC engine examines the voltage differences between the metal lines, and flags any VD-DRC violations. For a design to pass the VD-DRC checks, designers must know the MaxV and MinV voltage values on the nets, and attach these voltage values to the nets in the layout.

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