Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
EE Times-Asia > EDA/IP

Address DRC debug issues in 20nm custom designs

Posted: 19 Jul 2013 ?? ?Print Version ?Bookmark and Share

Keywords:design rule checks? DRC? double patterning? verification? Calibre RealTime?

Using traditional design techniques, the voltage values can be provided using either text on the geometries or marker layers. This information is then included in the GDSII that is passed to the verification tool. This technique is highly inefficient, as it requires designers to manually insert text on each of the nets, or add marker layers, both of which are time-consuming and prone to error. Also, designers are often not knowledgeable about the voltage values that should be present on the nets, which can lead to inaccurate values being used.

Using the Calibre RealTime/Laker integration (figure 2), designers complete the schematics for their design, and then run simulations on the schematics to generate a voltage table containing the MaxV and MinV voltage values present on each of the nets in the design. The voltage values are stored in the OpenAccess (OA) database in a view called the "constraint" view. When designers edit their layout design, Calibre RealTime reads the voltage values present on the nets in the layout from the OA constraint view, and processes this information in association with the layout geometries to generate the appropriate VD-DRC results.

Figure 2: VD-DRC flow in Synopsys Laker OpenAccess with Calibre RealTime.

This new flow requires that the net names in the schematic and layout views match so that, for a given net in the schematic, Calibre RealTime can find the corresponding net in the layout and apply the appropriate voltage values read from the constraint view. Designers can use the schematic-driven layout capability present in the design tool to ensure that there is a one-to-one correspondence for the net names between the schematic and layout views.

An example rule
An example is shown in figure 3, where the two metal lines have different MaxV and MinV values. The net on the left has a MaxV and MinV value of 3.3V, and the net on the right has a MaxV value of 6.6V and a MinV value of 5.5V. These voltage values were generated from the simulation runs launched on the schematic of the design. The VD-DRC check to be satisfied is: the spacing between two metal lines must be >1.5 microns when the difference between the MaxV present on one net and the MinV present on the neighbouring net is >3V. In our example, the voltage difference between the two metal lines is 3.3V and the spacing between the two metal-lines is

Figure 3: V Calibre RealTime identifies VD-DRC spacing violation.

To fix this VD-DRC violation, we must move one of the two metal lines such that that spacing between the two metal lines is >1.5 microns (figure 4).

Figure 4: Correction being applied to VD-DRC violation.

As soon as the right line is moved further away, Calibre RealTime immediately verifies in the design environment that the layout edit has corrected the VD-DRC violation by removing all error markers (figure 5).

Double patterning checks
At the 20 nm manufacturing node, double patterning (DP) is required, which means that in addition to the traditional DRC errors, designers must now understand and debug DP errors. One of the biggest challenges in DP design is to debug and correct DP violations.

?First Page?Previous Page 1???2???3???4?Next Page?Last Page

Article Comments - Address DRC debug issues in 20nm cus...
*? You can enter [0] more charecters.
*Verify code:


Visit Asia Webinars to learn about the latest in technology and get practical design tips.

Back to Top