Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
EE Times-Asia > EDA/IP

Address DRC debug issues in 20nm custom designs

Posted: 19 Jul 2013 ?? ?Print Version ?Bookmark and Share

Keywords:design rule checks? DRC? double patterning? verification? Calibre RealTime?

The most common double patterning error is an odd-cycle loop (also known as a ring). An odd cycle occurs when the spacing between an odd numbers of polygons is such that it requires the polygons to be on separate coloured masks relative to each other. However, with an odd number of polygons, there will always be two polygons of the same colour next to each other. The simplest case is a set of three polygons (figure 6), where each polygon must be a different colour from the other two. No matter how the designer tries to colour the polygons, it is not possible to create a DP-compliant layout with only two colours available.

Figure 5: Moving the two metal lines further apart corrects the VD-DRC violation.

Figure 6: A DP odd-cycle violation loop can never be resolved by changing colouring assignments.

The good news is that to fix an odd-cycle violation, designers only need to adjust one separation within the network of interacting polygons. The bad news is that there are three polygons, any one of which can be moved or adjusted. The problem with multiple options is that it is not obvious which option will provide the optimum fix. Also, fixing an odd-cycle violation can be both challenging and frustrating, because any edits made to fix one odd-cycle violation can create an entirely new odd-cycle violation involving the same polygons. With traditional design and verification flows, designers must often make multiple changes to multiple polygons before they can identify the optimum fix.

Figure 7 illustrates this scenario, where a simple odd cycle of three polygons abuts an even cycle of six polygons. The odd cycle is an error, while the even cycle is DP-compliant. The designer can increase the spacing of any of the three separators involved in the odd cycle in an attempt to fix the violation. However, if the designer chooses to fix the rightmost separator of the odd cycle, a new odd cycle of seven is created that now includes all of the polygons that were part of the original even cycle of six. This kind of "whack a mole" error propagation can be both infuriating and time-consuming.

Figure 7: Odd cycle propagation in DP violations is challenging to avoid with traditional DRC.

Double pattern debugging
Effective and efficient DP debugging for custom layout designers requires instantaneous signoff DRC feedback while they are correcting DP violations in the design environment. Instead of making edits, streaming out the GDSII, running DP checks, and then learning what impacts the changes have made, receiving real time DRC feedback in the design environment now allows designers to quickly perform "what-if" analysis on the design to deduce the optimum fix for these complex DP violations while they are still in the design phase.

In figure 8, a design is open in Laker and a Calibre RealTime run has reported an odd-cycle DP violation. The resulting output shows the two mask layers (highlighted in blue and green), the odd-cycle violation ring (highlighted in red) and warning rings (highlighted in yellow). When designers move the mouse over the error markers in the Laker environment, the description of the check generating the violations is shown in the yellow pop-up windows. Likewise, if they highlight a warning ring, they are advised that editing those shapes may cause the DP violation to expand. These types of "hints" greatly aid the designer to make fast, accurate choices when fixing DP cycle violations, and avoid creating new DP violations in the process.

Figure 8: DP odd-cycle violation loop displayed with associated warning rings and mask colours.

?First Page?Previous Page 1???2???3???4?Next Page?Last Page

Article Comments - Address DRC debug issues in 20nm cus...
*? You can enter [0] more charecters.
*Verify code:


Visit Asia Webinars to learn about the latest in technology and get practical design tips.

Back to Top