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Xilinx tapes out 20nm FPGA device

Posted: 11 Jul 2013 ?? ?Print Version ?Bookmark and Share

Keywords:3D IC? FPGA? ASIC?

Xilinx Inc. has revealed what it says is the semiconductor industry's first 20nm device, and the PLD industry's first 20nm All Programmable device. The company has also implemented what it boasts as the industry's first ASIC-class programmable architecture called UltraScale.

Xilinx has worked with TSMC to infuse high-end FPGA requirements into the TSMC 20SoC development process, just as it had done in the development of 28HPL. The 28nm collaboration resulted in the industry's first 28nm tape-out and the industry's first All Programmable FPGA, SoC, and 3D IC devices, putting Xilinx a generation ahead in price/performance/watt, programmable systems integration and BoM cost reduction, indicated the firm.

The UltraScale architecture was developed to scale from 20nm planar, through 16nm and beyond FinFET technologies, and from monolithic through 3D ICs. It not only addresses the limitations to scalability of total system throughput and latency, but directly attacks the number one bottleneck to chip performance at advanced nodes: the interconnect.

An innovative architectural approach is required to manage multi-hundred gigabit-per-second levels of system performance with smart processing at full line rate, scaling to terabits and teraflops. The mandate is not simply to increase the performance of each transistor or system block, or scale the number of blocks in the system, but to fundamentally improve the communication, clocking, critical paths and interconnect to address the massive data flow and real-time packet, DSP and/or image processing. The UltraScale architecture addresses these challenges by applying leading-edge ASIC techniques in a fully programmable architecture. These include massive data flow optimised for wide buses that support multi-terabit throughput; multi-region ASIC-like clocking, power management and next generation security; highly optimised critical paths and built-in high-speed memory, cascading to remove bottlenecks in DSP and packet processing; step function in inter-die bandwidth for 2nd generation 3D IC systems integration; massive I/O and memory bandwidth with dramatic latency reduction and 3D IC wide memory-optimised interface; and elimination of routing congestion and co-optimisation with Vivado tools for >90 per cent device utilisation without degradation in performance.

The initial UltraScale devices will extend the company's Virtex and Kintex FPGA and 3D IC families based on 28nm process technology, and will serve as the foundation for future Zynq UltraScale All Programmable SoCs. They will enable next generation smarter systems with new high-performance architectural requirements, including 400G OTN with intelligent packet processing and traffic management, 4X4 Mixed Mode LTE and WCDMA Radio with smart beamforming, 4K2K and 8K displays with smart image enhancement and recognition, highest performance systems for intelligence surveillance and reconnaissance (ISR) and high performance computing applications for the data centre.

Vivado Design Suite early access supporting UltraScale architecture-based FPGAs is now available. Initial UltraScale devices will be available in 4Q13.





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