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UMC adopts Cadence's DFM flows for 28nm node

Posted: 18 Jul 2013 ?? ?Print Version ?Bookmark and Share

Keywords:Cadence? UMC?

Cadence Design Systems has revealed that after extensive benchmark testing, semiconductor foundry United Microelectronics Corporation (UMC) has adopted the Cadence "in-design" and signoff design-for-manufacturing (DFM) flows to perform physical signoff and electrical variability optimisation for 28nm designs.

The flows address both random and systematic yield issues, providing customers with another proven foundry flow for 28nm designs. Developed in collaboration with UMC, these new flows incorporate DFM prevention, analysis, and signoff capabilities, including Cadence Litho Physical Analyser (LPA), Cadence Pattern Analysis, Cadence Litho Electrical Analyser (LEA), and Cadence Chemical-Mechanical Polishing Predictor (CCP) technologies.

"To meet our time-to-market goals, DFM solutions at 28nm need to deliver low cost of ownership, accurate silicon predictability and high performance," said S.C. Chien, vice president of IP & Design Support division at UMC. "After rigorous evaluation, the Cadence DFM technology was selected for its exceptional characteristics in both physical and electrical DFM analysis. Now, we can offer our customers much greater predictability and faster turnaround time for their advanced node designs."

UMC joins a growing list of leading foundries standardising on Cadence DFM solutions to boost productivity and yield for customers. The DFM signoff technologies tightly integrate into the Encounterdigital and Cadence Virtuoso custom/analogue implementation and sign-off solutions. This solution delivers a "correct-by-design" capability for customers that models and analyses the physical and parametric impact of lithography, Chemical-Mechanical Polishing (CMP), and layout dependent effects, and then optimises the implementation to mitigate the physical and electrical variation on the designs, allowing users to reach their time-to-volume goals.

"At advanced nodes, prevention of potential DFM hotspots and yield limiters before tape-out is imperative to achieving first-silicon success and the highest silicon yields," said Anirudh Devgan, corporate vice president, Silicon Realisation Group at Cadence. "Working in tight partnership with UMC, we continue to invest in technologies that strengthen our leadership in sign-off technologies, like providing DFM-aware implementation flows for current and future nodes."





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