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12bit, 80MSPS ADCs boast 3.5mW power consumption

Posted: 19 Jul 2013 ?? ?Print Version ?Bookmark and Share

Keywords:Synopsys? ADCs? data converter? LTE? WiFi?

Synopsys has debuted its 28nm data converter IP portfolio, which includes DesignWare analogue-to-digital converters (ADCs), digital-to-analogue converters (DACs) and integrated PLLs.

Implementing Synopsys' new data converter architecture in the 28nm process node resulted in up to 76 per cent reduction in power consumption and up to 86 per cent reduction in area use. The increase in Synopsys' 12bit ADCs' performance to 320 megasamples per second (MSPS) enables greater flexibility for system definition in communications applications such as those enabled by LTE and WiFi 802.11ac protocols.

"As the mobile industry moves to smaller SoC process nodes to meet consumer demand for higher performance, lower power consumption and smaller form factors, system architects are faced with a unique set of challenges that come with integrating 28nm analogue IP," said John Koeter, Synopsys' vice president of marketing for IP and systems.

Synopsys has introduced the successive approximation register (SAR)-based architecture for its 12bit high-speed ADCs. The ADCs currently offer conversion rates of up to 320 MSPS with architectural support for rates beyond 1 gigasample per second (GSPS). In addition, the 12bit high-speed DACs increase conversion rates to 600MSPS, a 50 per cent increase in speed over the previous generation. Increased conversion rates allow for higher oversampling of the signal, which reduces filtering requirements at the output of the DACs and simplifies the circuit design.





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