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Reduce SoC power use without high-level EDA tools

Posted: 30 Jul 2013 ?? ?Print Version ?Bookmark and Share

Keywords:SoC? register transfer language? RTL? EDA tools? coding?

Nowadays, design engineers face an arduous task of limiting power consumption in their SoC designs. More often than not, the complexities of designing for low power consumption are far removed from the EDA tools used in the backend design cycle. This gap can manifest in terms of interpretation of the tools, algorithms that are missing corner cases, or lack of support for the implementation of a particular design.

Thus, over-reliance on EDA tools might not always be a practical solution to low power concerns. It is always prudent to start the planning for power during the earliest stages of register transfer language (RTL) design. In this article we discuss several situations where the use of high level EDA tools are not useful and are sometimes a hindrance. We offer some techniques that can be used early at the RTL coding stage that will consume less power but keep the basic design intent unchanged.

Gating the clock
Clock Gating is the most commonly used design technique to save dynamic power consumed within the SoC. The entire SoC is seldom functional at any particular instant. Therefore, one can identify the possibilities where clock can be gated and make use of clock gating integrated cells. Consider the following RTL construct:

always @ (posedge clk or negedge reset)
??if (!reset)
????block_ff ??else if (block_enable)
block_ff Figure 1 shows the logical implementation and the corresponding low power clock-gated implementation that could be employed to save power.

Figure 1: Clock gated low power implementation.

Modern EDA tools identify such constructs and convert them into the clock-gated implementation shown in figure 1. However, it is not always desirable to get a gated clock structure from synthesis. It is possible that the enable condition (block_enable) may be "ON" so that implementing such a structure would augment the power consumption because the clock gating cell would itself consume some dynamic power. Even worse, the EDA tool might fail to discern such intent and not implement the clock gating structure where it could have indeed saved power.

EDA tools often see only what you tell them to see, so it is a better design practice to implement and insert clock gating cells in the RTL Itself, taking into account the actual use cases of when the particular block in question would be "ON" or "OFF".

Signal encoding
Designing finite state machines (FSMs) requires encoding the individual states, which can be a simple binary encoding, one-hot encoding, and grey encoding. Of these, Grey encoding leads to a design which consumes lower power as compared to binary encoding, as discussed below.

As shown in figure 2, in Grey Encoding any two adjacent states differ in only 1 bit. Hence, during the normal operation of the FSM, there are fewer transitions as the FSM moves from one state to another, resulting in lower power consumption. While designing a higher order Grey Counter might be a tedious task, for lower order counter (up to 4 bits and 16 states), this encoding scheme can be employed to save power without incurring any additional design complexity.

Figure 2: State encoding.

Fixing redundant transitions by operand isolation
One can save considerable dynamic power by fixing the redundant transitions in the design. However, the key lies in identifying those structures and designing with the goal of low power in mind. Consider the simple design of an Arithmetic Logic Unit which includes an adder and a multiplier, shown in figure 3.

Figure 3: Simple ALU.

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