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SpeedBridge adapter enables PCIe 3.0 design verification

Posted: 31 Jul 2013 ?? ?Print Version ?Bookmark and Share

Keywords:Cadence Design? PCIe? adapter? pre-silicon environment?

Cadence Design Systems recently unveiled a new SpeedBridge Adapter for PCIe 3.0. The adapters provides easy bring-up and fast debug of PCIe-based designs when used with a Cadence Palladium Verification Computing Platform, and is backwards compatible with PCIe 2.0-, 1.1- and 1.0a-based designs. The SpeedBridge Adapter for PCIe 3.0 reduces time to market and system risk for complex designs by providing high-speed interaction with real-world traffic in a pre-silicon environment running production-level software drivers and an OS.

"Increasingly, designers are faced with a difficult balancing act of managing increasing design complexities and shrinking time-to-market windows," said Christopher Tice, corporate vice president, Hardware System Verification, System and Software Realisation Group at Cadence. "PCIe 3.0 has increased complexity levels including higher data transfer rates, backwards compatibility requirements, and different standards for equalisation. In order to prevent costly re-spins and time-to-market delays, it is imperative for designers to perform complete system verification under complex real-world conditions with high fidelity full-speed interfaces."

The SpeedBridge Adapter is designed for pre-silicon RTL and integration of PCIe-based ASICs and systems-on-chip (SoCs) and allows system emulation under real-world operating conditions. The adapter verifies emulated PCIe 3.0 designs with the actual ASIC or SoC software and hardware, driver and application development, and runs with existing software and software test programs or analyser.





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