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Creating hybrid FPGA/virtual platform prototypes

Posted: 08 Aug 2013 ?? ?Print Version ?Bookmark and Share

Keywords:SoC? PCI Express? PCIe? Cabling? SystemC/TLM?

FPGA-based prototypes deliver high value to a SoC development organisation by providing multi-megahertz processing performance, real world I/O connectivity, and portability for distribution to software developers or field testing scenarios. The prototypes deliver operational systems running fast enough to make embedded software development and hardware/software validation feasible. Teams that have adopted FPGA-based prototyping realise months in shortened schedules and a more efficient and parallel hardware/software engineering methodology.

To fully realise the potential of these systems and maximise the return on investment from prototyping systems, development teams are taking advantage of advanced data exchange links beyond traditional JTAG. High-bandwidth physical links like PCI Express (PCIe) over Cabling allow the prototype to communicate with custom user applications for system control and monitoring. With a transaction-level interface to a SystemC/TLM virtual prototype, a new class of hybrid prototype is possible that leverages the strengths of both hardware and software-based prototyping methods.

Providing connectivity for a prototyping system
The conventional usage of the FPGA-based prototype has been as a stand-alone, isolated system. Any data links to a workstation have been relegated to programming the FPGA devices via JTAG, or in cases where an embedded CPU is included, a JTAG debug port allows the embedded software debug environment to communicate with the prototype for memory monitoring and source code debug. JTAG is an excellent vehicle for occasional data access, but it was not designed for high-bandwidth communication.

PCI Express expansion by using PCIe over Cabling products (figure 1) has emerged as a de facto standard to provide higher bandwidth data exchange with FPGA-based prototypes. Most commercial FPGA-based prototyping systems provide some manner of PCIe access. For example, the UMRBus incorporated into the Synopsys HAPS 60 FPGA-based prototyping system provides the hardware infrastructure, OS device drivers, and various APIs for configuration and data exchange.

Figure 1: Example physical connectivity for FPGA-based prototype, Synopsys UMRBus PCIe over Cable.

Synopsys FPGA-based prototype
To maximise versatility and application, the UMRBus was designed as a multi-point interface. The plaform supports 27 independent interfaces per hardware motherboard and each interface provides 63 independently addressable interfaces per UMRBus chain. This deep hardware capacity allows the communication system to access various regions of the ASIC/SoC design and commit a communication channel for a particular application of the bus.

OS-specific APIs consist of functions for a host application to access client applications of the prototype. Depending on the application and bandwidth demand, the UMRBus provides data width options of 1-, 2-, 4-, 8-, 16-, and 32bit implementations. An 800 Mbit/s performance is possible given a 100MHz global system clock and an 8bit wide configuration.

Now that we have a high-performance, low-latency channel between the workstation and the prototype new hardware/software validation scenarios are possible and benefits can be realised with the communication link.

A rapid update process for boot ROM firmware
Consider a scheme for applying updates to the embedded boot ROM firmware of an FPGA-based prototype. In an embedded system, at the time of power on the CPU is uninitialized and system-specific configuration is required before proceeding to complex tasks like loading the embedded operating system. A piece of code is required at power-on that does the basic system setup before handing over the control to the boot loader usually present in external NOR/NAND Flash memory or to support the download tool for programming the Flash.

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