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DCD's Soft IP core supports 8MB linear code space

Posted: 02 Aug 2013 ?? ?Print Version ?Bookmark and Share

Keywords:Digital Core Design? IP core? RISC architecture? FPGA?

Digital Core Design recently unveiled the DP80390 soft IP Core, a high performance, speed optimised soft core of a single-chip 8bit embedded controller intended to operate with fast (typically on-chip) and slow (off-chip) memories. It is 100 per cent binary compatible with 8051 and 80390 instruction sets.

The DP80390 boasts a pipelined RISC architecture executes up to 200 million instructions per second and consumes just 8120 gates. It is a technology independent IP Core, allowing easy implementation in both ASIC and FPGA. The core also supports up to 8MB of linear code space and 16MB of linear data space.

The pipelined RISC architecture of the DP80390 executes 85 C 200 million instructions per second, running the Dhrystone 2.1 benchmark from 11.46 to 15.55 times faster than the original 80C51 at the same frequency.

The soft IP Core is delivered with fully automated test bench and complete set of tests, allowing easy package validation at each stage of SoC design flow. Each of DCD's 80390 Cores has built in support for the DCD's Hardware Debug System, called DoCD. It is a real-time hardware debugger, which provides debugging capability of a whole System-on-Chip.

Unlike other on-chip debuggers, the DoCD provides non-intrusive debugging of running application. It can halt, run, step into or skip an instruction, read/write any contents of microcontroller, including all registers, internal and external program memories and all SFRs, including user defined peripherals.

More information about the DP80390 can be accessed here.

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