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Cadence unveils VIP Models for latest memory standards

Posted: 08 Aug 2013 ?? ?Print Version ?Bookmark and Share

Keywords:Cadence? memory standards? LPDDR4? eMMC?

During the recent MemCon 2013, Cadence Design Systems announced the availability of its new verification IP (VIP) models for its latest memory standards, the LPDDR4, Wide I/O 2, eMMC 5.0, HMC and DDR4 LRDIMM.

"Memory is playing an important role in the increased functionality and performance of mobile devices such as smartphones and tablets," said Mian Quddus, chairman of the JEDEC Board of Directors. "LPDDR4 and Wide I/O 2 are key new standards for memory interfaces, and the availability of memory models will allow designers to take advantage of these standards quickly."

Cadence's latest models feature trace debug, address scrambling and backdoor memory access. The models also support all leading third party simulators, verification languages and methodologies enabling SoC designers to verify the correctness of interfaces to these new, specialised memories.

"There's a new dynamic today in which designers are faced with more standards being introduced but with shorter lifecycles. At the same time, they need to address power, performance, cost, thermal and packaging constraints," said Martin Lund, Cadence's senior vice president. "To address this, we are providing access to models supporting as many standards options as possible, so designers can get to market success as fast as possible."





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