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Tabula's stylus compiler adds SystemVerilog support

Posted: 15 Aug 2013 ?? ?Print Version ?Bookmark and Share

Keywords:Verific? Tabula? SystemVerilog?

Verific Design Automation has revealed that that Tabula has added Verific's SystemVerilog parser as front-end support to version 2.7.1 of its Stylus compiler.

Tabula, advancing high-performance programmable logic solutions for network infrastructure systems, announced that its recently released version of the Stylus compiler can process code written with SystemVerilog syntax through the use of the SystemVerilog parser.

"Verific's SystemVerilog and VHDL parsers are among the best architected and implemented software packages in EDA," says Karen Pieper, Tabula's director of software, who has extensive experience parsing Verilog and VHDL. "Our upgrade from Verilog to SystemVerilog went extremely smoothly."

Verific's software serves as the front end to a wide range of EDA and field programmable gate array (FPGA) tools for analysis, simulation, verification, synthesis, emulation and test of register transfer level (RTL) designs. Verific's Parser Platform includes support for SystemVerilog, Verilog, VHDL and UPF, and provides C++ and Perl application programming interfaces (APIs). Verific's software is distributed as C++ source code and compiles on all 32- and 64bit Unix, Linux and Windows operating systems.





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