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Cadence Encounter used to tape-out Freescale's T4240 SoC

Posted: 19 Aug 2013 ?? ?Print Version ?Bookmark and Share

Keywords:Cadence Design Systems? Freescale? EDI? processors?

Cadence Design Systems recently unveiled that Freescale Semiconductor used the latest release of Encounter Digital Implementation (EDI) System to tape-out its next generation QorIQ T4240 system on chip (SoC) running at 1.8GHz. The T4240 is based on multiple 64bit Power Architecture clusters of high-performance e6500 processors and modern system peripherals.

"Our T4240 SoC represents a great step forward in our high-performance QorIQ T series product line targeted for demanding networking applications. Cadence's GigaOpt technology helped us achieve aggressive time to market for our next generation T4240 SoC," said Ken Hansen, vice president and chief technology officer, Freescale Semiconductor. "We were also able to realise better design performance, smaller silicon area, and improve design team productivity."

Freescale's QorIQ processing platforms are complete SoCs for networking applications across carrier, enterprise cloud computing, military, and industrial markets. The highly integrated T4240 SoC has a complex floorplan with multiple hierarchical blocks, 12 Power Architecture 64bit processors, high-speed I/O, on-chip networking, high-speed cache coherency interconnect fabric, and complex clocking schemes, requiring high performance and power efficiency.

GigaOpt is a new multi-threaded physical optimisation technology included as standard in the latest EDI System release for pre-route, post-clock tree synthesis, and post-route optimisation. GigaOpt also includes new layer-aware timing-driven net buffering and critical path replacement algorithms which deliver significant improvements in design performance, area, and power.

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