Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
?
EE Times-Asia > Interface
?
?
Interface??

Evaluating your design's high-speed interconnects

Posted: 23 Aug 2013 ?? ?Print Version ?Bookmark and Share

Keywords:Signal integrity? RF board? electromagnetic? SI? Universal Serial Bus?

Signal integrity (SI) addresses two crucial aspects of high-speed digital designs: signal timing and quality. SI analysis aims to ensure signals reach their destination in good condition.

In a system, signals travel through various kinds of interconnections (e.g., from chip to package, package to RF board trace and trace to high-speed connectors), with any electrical impact happening at the source end, along the transmission path or at the receiving end, which affects both signal timing and quality. Connector performance directly affects system performance and reliability. As a result, designing and modelling connectors for multi-gigabit applications is one of the greatest challenges in high-speed digital applications.

When designing high-speed applications, signal transmission quality is a critical factor. At gigabit speeds, high-speed interconnects must be characterized along with the RF board traces. Ever-increasing demand for cleaner signal transmission means that maintaining good signal quality throughout the high-speed interconnects is crucial.

Modern high-speed, multi-pin connectors are required to enable data transmission in systems at a very high rate (~ 5Gbit/s). Early design changes based on accurate simulations can be indispensable and worthy investments for interconnect realisation. Likewise, use of an accurate electromagnetic (EM) model is highly desirable during the design and implementation stage of high-speed interconnects. To achieve good SI, the designer must not only understand the system in which the connectors will be deployed, but also perform SI analysis of the RF board along with the connectors.

Figure 1: The design flow used to model the SATA to USB data transfer module using ADS and EMPro, a 3D electromagnetic solver with both time- and frequency-domain based EM solvers.

Figure 2: This image depicts (top) a 3D EMPro model and pins of the SATA connector and (bottom) simulated return and insertion loss plots.

The hybrid approach
Over the years, various 3D interconnect simulation techniques have emerged to improve the integrated circuit density and operation speed of multi-layer, very large, high-speed board integration designs. However, these techniques often lead to impedance discontinuities that induce SI/power integrity and electromagnetic interference effects when the RF board and connectors are simulated separately.

One way to address this challenge is with hybrid EM simulation. Essentially, with this approach, the connectors (or other 3D components) are integrated with the RF board and simulated together using planar and 3D EM simulation along with a transient solver. The planar simulation is based on a finite element method (FEM) solver, while the EM simulation relies on a method of moment (MoM) solver.

To better understand how this hybrid approach works, consider the design and analysis of a serial ATA (SATA) to Universal Serial Bus (USB) data transfer module. Signals originating from the SATA connector go through two pairs of differential lines to a data transfer chip package. From the chip package, signals go to the USB connector through two pairs of differential lines routed on two different layers. The connectors, chip packages and printed circuit boards form electrical paths on which to conduct the SI analysis.

1???2???3?Next Page?Last Page



Article Comments - Evaluating your design's high-speed ...
Comments:??
*? You can enter [0] more charecters.
*Verify code:
?
?
Webinars

Seminars

Visit Asia Webinars to learn about the latest in technology and get practical design tips.

?
?
Back to Top