Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
EE Times-Asia > Manufacturing/Packaging

Embedded packaging cuts PoP height by 40%

Posted: 22 Aug 2013 ?? ?Print Version ?Bookmark and Share

Keywords:embedded packaging? Package-on-Package? eWLB?

STATS ChipPAC Ltd has revealed what it boasts as an achievement in reducing Package-on-Package (PoP) height with its ultra thin embedded Wafer Level Ball Grid Array (eWLB) technology. Through further innovations in eWLB technology, the firm has reached a 40 per cent height reduction in the bottom PoP architecture to provide an ultra thin z-height of 0.3mm, providing customers with the advantage of having an overall PoP package height as low as 0.8mm with proven board level reliability, the company stated.

The industry adoption of PoP as a dominant packaging approach in stacking the logic processor and memory into a single solution for advanced mobile phones and tablets has accelerated the need to drive ultra thin package profiles in this technology. Earlier in 2012, STATS ChipPAC used eWLB technology to deliver a 30 per cent height reduction in PoP, reducing the overall stacked package height from the industry standard 1.4mm to 1mm.

eWLB provides a robust packaging platform supporting ultra high density interconnection and routing of multiple die in very reliable, low-profile, low-warpage packages that are cost effective solutions for baseband processors, RF transceivers, power management components and application processors. For high performance applications such as smartphones and tablets, eWLB technology delivers fine line width and spacing of less than 10um/10um as well as superior electrical performance, providing more design flexibility and a more significant reduction in size than is possible with PCB substrate technology.

Article Comments - Embedded packaging cuts PoP height b...
*? You can enter [0] more charecters.
*Verify code:


Visit Asia Webinars to learn about the latest in technology and get practical design tips.

Back to Top