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Achieve successful timing closure

Posted: 27 Aug 2013 ?? ?Print Version ?Bookmark and Share

Keywords:SOC? timing optimisation? physical design? PLL? jitter?

With the rapid technology developments, the complexity of design is increasing from day to day. To meet lower technology challenges and to achieve good silicon yield, SOC design flows have been enhanced and have introduced more number of design implementations steps. With every implementation step which takes design towards realistic working silicon, SOC design timing performance degrades due to various factors which were not apparent at previous implementation step. Thus it is very important to have a right estimate of design frequency since first stage of design implementation. The important parameter which makes it possible are called Design Margins.

Design margins
Design Margins are the extra pessimism introduced in terms of design uncertainty which covers the expected timing hit of every stage in implementation cycle so as to achieve targeted frequencies well in time. It is very much required to have a right estimate of design margins.

Underestimated design margins
The scope of timing optimisation reduces as we move down the implementation flow. So it becomes very important to judge the setup timing degradation hit in advance to achieve the targeted design frequency at the end. If design margins are not enough for any stage, it will not be possible to close design targeted frequencies. It will directly impact Design Performance.

Overestimated design margins
For any stage if design margins are chosen overly pessimistic, it will result in extra timing optimisation which might not be required. This results in extra consumption of silicon area and power. The impact is SOC designs would not be cost effective, also bad power numbers may result in poor battery life.

General SOC flow and impact on design frequency
Figure 1 shows general SOC flow which starts from synthesis and concludes at noise closure.

Figure 1: General SOC closure flow.

The first step of physical design SOC closure flow is synthesis. During synthesis stage the exact timing degradation due to placement, clock skew, inter connect delays and noise is not known. So, during synthesis stage timing uncertainty corresponding to above parameters has to be modelled properly for efficient timing closure. So, effective frequency for a timing path is maximum at synthesis stage. Now, at placement stage the designer is aware of timing degradation because of placement but not due to clock skew, inter connect delays and noise. So, at placement stage timing uncertainty need not include placement margin. Based on the above reasoning, it is clear that timing uncertainty should be different at different stages of the design.

Timing margins (uncertainties) for different design stages
PLL Jitter: PLL Jitter value, which indicates the edge shift of PLL clock from one edge to another, is very crucial factor while timing setup path. It can either be considered in uncertainty or can be made part of clock period. Making it a part of clock period make more sense as it should be adjusted in case of multi cycle paths

2 Types: Cycle2Cycle Jitter: Jitter between 2 consecutive edges
Long Term Jitter: It provides maximum possible jitter to be considered for multiple cycle paths.

To maintain pessimism in correct way, it is better to make it a part of clock period. And for multi cycle path it can always be checked whether [N x (cycle2cycle jitter)] or long term jitter should be considered, where N is the multi cycle value.

Half Cycle Jitter: Half cycle jitter specifies the edge shift between rise and fall edges. All half cycle paths should be closed after factoring this half cycle jitter uncertainty

Placement timing jump
Since physical location of design instances is not known during logical synthesis stage, the timing degradation is bound to happen while moving from synthesis to placement stage. Moreover the synthesis tool generally has better logic optimisation capability, so it is better to keep extra timing margin at synthesis stage (which is removed at placement stage), to negate the timing degradation impact because of placement.

Clock skew
Clock skew determines the allowed skew while clock tree synthesis. Too low skew numbers can lead to increase in clock latency and can impact us with increased OCV effect and dynamic power, and at the same time too relaxed skew targets can cause too many hold violations.

Maximum Range can be figured out by using following formula for a typical hold critical path.

Skew (max) Above value should be justified with minimum latency of clock.

Note:
???CTS tools generally work in single operating mode. But, as the signoff analysis is always done in OCV mode, clock skew should be measured after switching to OCV mode.
???In case of clocks with different top level source latency, we also need to have inter clock skew uncertainty.

OCV margin
Various factors for On Chip Variations are

???IR drop.
???Layer to layer metallisation mismatch.
???CMP induced metallisation variations.
???Transistor level Vth mismatch.
???Transistor level mobility mismatch.
???Intra die temperature variation.
???Toggling activity mismatch (related to transistor ageing).

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